[PATCH] D50252: [ARM] Added Codegen support for vrev64q_f16 8xf16 and vextq_f16 8xf16 vector intrinsics

[Luke Geeson via Phabricator via llvm-commits]

LukeGeeson created this revision.
LukeGeeson added a reviewer: SjoerdMeijer.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

In detail it adds support for test_vrev64q_f16 and test_vextq_f16 tests from test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

In line with Sjoerd Meijers' bug hunting report: https://bugs.llvm.org/show_bug.cgi?id=38404 and https://reviews.llvm.org/rL338568

I have not committed the 4xf16 intrinsics yet as I am awaiting the result of https://reviews.llvm.org/D49987.


Repository:
  rL LLVM

https://reviews.llvm.org/D50252

Files:
  lib/Target/ARM/ARMInstrNEON.td
  test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll


Index: test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
===================================================================
--- test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -1141,23 +1141,24 @@
 ;  ret <4 x half> %vext
 ;}
 ;
-;define dso_local <8 x half> @test_vextq_f16(<8 x half> %a, <8 x half> %b) {
-;entry:
-;  %vext = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
-;  ret <8 x half> %vext
-;}
+define dso_local <8 x half> @test_vextq_f16(<8 x half> %a, <8 x half> %b) {
+entry:
+  %vext = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
+  ret <8 x half> %vext
+}
+; FIXME (PR38404)
 ;
 ;define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
 ;entry:
 ;  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 ;  ret <4 x half> %shuffle.i
 ;}
 ;
-;define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
-;  ret <8 x half> %shuffle.i
-;}
+define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x half> %shuffle.i
+}
 
 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
Index: lib/Target/ARM/ARMInstrNEON.td
===================================================================
--- lib/Target/ARM/ARMInstrNEON.td
+++ lib/Target/ARM/ARMInstrNEON.td
@@ -6564,6 +6564,7 @@
 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
+def : Pat<(v8f16 (NEONvrev64 (v8f16 QPR:$Vm))), (VREV64q16 QPR:$Vm)>;
 
 //   VREV32   : Vector Reverse elements within 32-bit words
 
@@ -6682,6 +6683,12 @@
                            (i32 imm:$index))),
           (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
 
+
+def : Pat<(v8f16 (NEONvext (v8f16 QPR:$Vn),
+                           (v8f16 QPR:$Vm),
+                           (i32 imm:$index))),
+          (VEXTq16 QPR:$Vn, QPR:$Vm, imm:$index)>;
+
 //   VTRN     : Vector Transpose
 
 def  VTRNd8   : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;


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