[PATCH] D49966: [X86] Performing DAG pruning before selection of LEA instructions.

[Jatin Bhateja via Phabricator via llvm-commits]

jbhateja added inline comments.


================
Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:725-728
+      // Following transformation is being done
+      // %1 = SHL X , 2       ->   %1 = SUB 0 , Y
+      // %2 = SUB %1 , Y           %2 = SHL X , 2
+      //                           %3 = ADD %2 , %1
----------------
lebedev.ri wrote:
> This turned out hard to read. Can you replace it with
> ```
> %o0 = shl i8 %x, C   ->  %n0 = sub i8 0, %y
> %r = sub i8 %o0, %y      %n1 = shl i8 %x, C
>                          %r = add i8 %n1, %n0
> ```
> 
Optimization has been limited to i32 and i16, i8 optimization is correct but LEA extraction is being done only for 32 and 64 bits types. On way is to promote i8 types to i32 type which will trigger LEA selection and then truncate result to i8 , this is what is being done for i16.  


```
/// Return true if the target has native support for the specified value type
/// and it is 'desirable' to use the type for the given node type. e.g. On x86
/// i16 is legal, but undesirable since i16 instruction encodings are longer and
/// some i16 instructions are slow.
bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
  if (!isTypeLegal(VT))
    return false;

  // There are no vXi8 shifts.
  if (Opc == ISD::SHL && VT.isVector() && VT.getVectorElementType() == MVT::i8)
    return false;

**  if (VT != MVT::i16)
    return true;**
```


Repository:
  rL LLVM

https://reviews.llvm.org/D49966