[llvm] r338554 - [AArch64] Fix FCCMP with FP16 operands

[Hans Wennborg via llvm-commits]

Merged to 7.0 in r338692.

On Wed, Aug 1, 2018 at 3:50 PM, Bryan Chan via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: bryanpkc
> Date: Wed Aug  1 06:50:29 2018
> New Revision: 338554
>
> URL: http://llvm.org/viewvc/llvm-project?rev=338554&view=rev
> Log:
> [AArch64] Fix FCCMP with FP16 operands
>
> Summary: This patch adds support for FCCMP instruction with FP16 operands, avoiding an assertion during instruction selection.
>
> Reviewers: olista01, SjoerdMeijer, t.p.northover, javed.absar
>
> Reviewed By: SjoerdMeijer
>
> Subscribers: kristof.beyls, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D50115
>
> Modified:
>     llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
>     llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=338554&r1=338553&r2=338554&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Wed Aug  1 06:50:29 2018
> @@ -4639,7 +4639,9 @@ class BaseFPCondComparison<bit signalAll
>
>  multiclass FPCondComparison<bit signalAllNans, string mnemonic,
>                              SDPatternOperator OpNode = null_frag> {
> -  def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic, []> {
> +  def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic,
> +      [(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm), (i32 imm:$nzcv),
> +                          (i32 imm:$cond), NZCV))]> {
>      let Inst{23-22} = 0b11;
>      let Predicates = [HasFullFP16];
>    }
>
> Modified: llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll?rev=338554&r1=338553&r2=338554&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll Wed Aug  1 06:50:29 2018
> @@ -456,6 +456,36 @@ define i1 @test_fcmp_ord(half %a, half %
>    ret i1 %r
>  }
>
> +; CHECK-COMMON-LABEL: test_fccmp:
> +; CHECK-CVT:      fcvt  s0, h0
> +; CHECK-CVT-NEXT: fmov  s1, #8.00000000
> +; CHECK-CVT-NEXT: fmov  s2, #5.00000000
> +; CHECK-CVT-NEXT: fcmp  s0, s1
> +; CHECK-CVT-NEXT: cset  w8, gt
> +; CHECK-CVT-NEXT: fcmp  s0, s2
> +; CHECK-CVT-NEXT: cset  w9, mi
> +; CHECK-CVT-NEXT: tst   w8, w9
> +; CHECK-CVT-NEXT: fcsel s0, s0, s2, ne
> +; CHECK-CVT-NEXT: fcvt  h0, s0
> +; CHECK-CVT-NEXT: str   h0, [x0]
> +; CHECK-CVT-NEXT: ret
> +; CHECK-FP16:      fmov  h1, #5.00000000
> +; CHECK-FP16-NEXT: fcmp  h0, h1
> +; CHECK-FP16-NEXT: fmov  h2, #8.00000000
> +; CHECK-FP16-NEXT: fccmp h0, h2, #4, mi
> +; CHECK-FP16-NEXT: fcsel h0, h0, h1, gt
> +; CHECK-FP16-NEXT: str   h0, [x0]
> +; CHECK-FP16-NEXT: ret
> +
> +define void @test_fccmp(half %in, half* %out) {
> +  %cmp1 = fcmp ogt half %in, 0xH4800
> +  %cmp2 = fcmp olt half %in, 0xH4500
> +  %cond = and i1 %cmp1, %cmp2
> +  %result = select i1 %cond, half %in, half 0xH4500
> +  store half %result, half* %out
> +  ret void
> +}
> +
>  ; CHECK-CVT-LABEL: test_br_cc:
>  ; CHECK-CVT-NEXT: fcvt s1, h1
>  ; CHECK-CVT-NEXT: fcvt s0, h0
>
>
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