[PATCH] D49987: [ARM] Allow half-precision FP softening

[Mikhail Maltsev via Phabricator via llvm-commits]

miyuki created this revision.
miyuki added reviewers: olista01, eli.friedman.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

On targets that do not support FP16 natively LLVM currently legalizes
vectors of FP16 values by scalarizing them and promoting to FP32. This
causes problems for the following code:

  void foo(int, ...);
  
  typedef __attribute__((neon_vector_type(4))) __fp16 float16x4_t;
  void bar(float16x4_t x) {
    foo(42, x);
  }

According to the AAPCS (appendix A.2) float16x4_t is a containerized
vector fundamental type, so 'foo' expects that the 4 16-bit FP values
are packed into 2 32-bit registers, but instead bar promotes them to
4 single precision values.

This patch allows FP16 vectors to be "softened", i.e. bitcast to
16-bit integer vectors when needed. The change required several
adjustments in SelectionDAG and in ARM FP16 tests.


https://reviews.llvm.org/D49987

Files:
  lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  test/CodeGen/ARM/fp16-promote.ll
  test/CodeGen/ARM/fp16-soften.ll
  test/CodeGen/ARM/fp16-v3.ll
  test/Transforms/LoopVectorize/ARM/interleaved_cost.ll

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