[llvm] r338129 - [AArch64] add more tests for signbit math; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Jul 27 09:21:56 2018
New Revision: 338129

URL: http://llvm.org/viewvc/llvm-project?rev=338129&view=rev
Log:
[AArch64] add more tests for signbit math; NFC

Modified:
    llvm/trunk/test/CodeGen/AArch64/signbit-shift.ll

Modified: llvm/trunk/test/CodeGen/AArch64/signbit-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/signbit-shift.ll?rev=338129&r1=338128&r2=338129&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/signbit-shift.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/signbit-shift.ll Fri Jul 27 09:21:56 2018
@@ -27,6 +27,20 @@ define i32 @add_zext_ifpos(i32 %x) {
   ret i32 %r
 }
 
+define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: add_zext_ifpos_vec_splat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT:    cmgt v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.4s, #41
+; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    ret
+  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = zext <4 x i1> %c to <4 x i32>
+  %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
+  ret <4 x i32> %r
+}
+
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       // %bb.0:
@@ -63,6 +77,20 @@ define i32 @add_sext_ifpos(i32 %x) {
   ret i32 %r
 }
 
+define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: add_sext_ifpos_vec_splat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT:    cmgt v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.4s, #42
+; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = sext <4 x i1> %c to <4 x i32>
+  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
+  ret <4 x i32> %r
+}
+
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       // %bb.0:
@@ -145,3 +173,56 @@ define i32 @sel_ifneg_fval_bigger(i32 %x
   ret i32 %r
 }
 
+define i32 @add_lshr_not(i32 %x) {
+; CHECK-LABEL: add_lshr_not:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvn w8, w0
+; CHECK-NEXT:    lsr w8, w8, #31
+; CHECK-NEXT:    add w0, w8, #41 // =41
+; CHECK-NEXT:    ret
+  %not = xor i32 %x, -1
+  %sh = lshr i32 %not, 31
+  %r = add i32 %sh, 41
+  ret i32 %r
+}
+
+define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: add_lshr_not_vec_splat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvn v0.16b, v0.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #31
+; CHECK-NEXT:    orr v0.4s, #42
+; CHECK-NEXT:    ret
+  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
+  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
+  ret <4 x i32> %r
+}
+
+define i32 @sub_lshr_not(i32 %x) {
+; CHECK-LABEL: sub_lshr_not:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvn w8, w0
+; CHECK-NEXT:    mov w9, #43
+; CHECK-NEXT:    sub w0, w9, w8, lsr #31
+; CHECK-NEXT:    ret
+  %not = xor i32 %x, -1
+  %sh = lshr i32 %not, 31
+  %r = sub i32 43, %sh
+  ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_not_vec_splat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvn v0.16b, v0.16b
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #31
+; CHECK-NEXT:    movi v1.4s, #42
+; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    ret
+  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
+  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+  ret <4 x i32> %r
+}
+