[llvm] r338121 - [AArch64][SVE] Asm: Support for FEXPA and FTSSEL.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 27 05:40:09 PDT 2018
Author: s.desmalen
Date: Fri Jul 27 05:40:09 2018
New Revision: 338121
URL: http://llvm.org/viewvc/llvm-project?rev=338121&view=rev
Log:
[AArch64][SVE] Asm: Support for FEXPA and FTSSEL.
This patch adds support for transcendental acceleration
instructions 'FEXPA' (exponential accelerator) and 'FTSSEL'
(trigonometric select coefficient).
Added:
llvm/trunk/test/MC/AArch64/SVE/fexpa-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fexpa.s
llvm/trunk/test/MC/AArch64/SVE/ftssel-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ftssel.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=338121&r1=338120&r2=338121&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Fri Jul 27 05:40:09 2018
@@ -135,6 +135,8 @@ let Predicates = [HasSVE] in {
defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">;
defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">;
+ defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">;
+
defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">;
@@ -199,6 +201,10 @@ let Predicates = [HasSVE] in {
def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">;
def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">;
+ def FEXPA_ZZ_H : sve_int_bin_cons_misc_0_c<0b01000000, "fexpa", ZPR16>;
+ def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>;
+ def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>;
+
def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=338121&r1=338120&r2=338121&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Fri Jul 27 05:40:09 2018
@@ -3959,3 +3959,48 @@ multiclass sve_int_bin_cons_misc_0_a_64_
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>;
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>;
}
+
+
+//===----------------------------------------------------------------------===//
+// SVE Integer Misc - Unpredicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
+ asm, "\t$Zd, $Zn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zd;
+ bits<5> Zm;
+ bits<5> Zn;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Zm;
+ let Inst{15-10} = 0b101100;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sve_int_bin_cons_misc_0_b<string asm> {
+ def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>;
+ def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>;
+ def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>;
+}
+
+class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins zprty:$Zn),
+ asm, "\t$Zd, $Zn",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zd;
+ bits<5> Zn;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = opc{7-6};
+ let Inst{21} = 0b1;
+ let Inst{20-16} = opc{5-1};
+ let Inst{15-11} = 0b10111;
+ let Inst{10} = opc{0};
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
\ No newline at end of file
Added: llvm/trunk/test/MC/AArch64/SVE/fexpa-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fexpa-diagnostics.s?rev=338121&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fexpa-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fexpa-diagnostics.s Fri Jul 27 05:40:09 2018
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+fexpa z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fexpa z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fexpa z0.s, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fexpa z0.s, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
Added: llvm/trunk/test/MC/AArch64/SVE/fexpa.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fexpa.s?rev=338121&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fexpa.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fexpa.s Fri Jul 27 05:40:09 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fexpa z0.h, z31.h
+// CHECK-INST: fexpa z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0xbb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bb 60 04 <unknown>
+
+fexpa z0.s, z31.s
+// CHECK-INST: fexpa z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bb a0 04 <unknown>
+
+fexpa z0.d, z31.d
+// CHECK-INST: fexpa z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bb e0 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ftssel-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ftssel-diagnostics.s?rev=338121&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ftssel-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ftssel-diagnostics.s Fri Jul 27 05:40:09 2018
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+ftssel z0.b, z1.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ftssel z0.b, z1.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
Added: llvm/trunk/test/MC/AArch64/SVE/ftssel.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ftssel.s?rev=338121&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ftssel.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ftssel.s Fri Jul 27 05:40:09 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ftssel z0.h, z1.h, z31.h
+// CHECK-INST: ftssel z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xb0,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 b0 7f 04 <unknown>
+
+ftssel z0.s, z1.s, z31.s
+// CHECK-INST: ftssel z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xb0,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 b0 bf 04 <unknown>
+
+ftssel z0.d, z1.d, z31.d
+// CHECK-INST: ftssel z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xb0,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 b0 ff 04 <unknown>
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