[PATCH] D49836: AMDGPU: Remove broken ternary i16 patterns

[Jan Vesely via Phabricator via llvm-commits]

jvesely added inline comments.


================
Comment at: lib/Target/AMDGPU/VOP3Instructions.td:469-474
-def : GCNPat<
-  (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
-   (REG_SEQUENCE VReg_64,
-     (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)), sub0,
-     (V_MOV_B32_e32 (i32 0)), sub1)
->;
----------------
jvesely wrote:
> arsenm wrote:
> > These can be fixed, they don't need to be dropped.
> > 
> > It's also more complicated because since gfx9 there is a control bit for whether the high 16-bits are zeroed or preserved which we haven't implemented
> There is no reason to preserve and fix them since they'd need to be the same instructions which end up being used anyway. There is nothing to be gained from having the extension part in the pattern.
> 
> the gfx9 part does not apply you can drop zero_extend if v_mad_i16  clears those bits, but that should not be handled in this pattern.
In fact including the extension op here would be damaging. Leaving it outside exposes it to other patterns that could replace or eliminate it.


Repository:
  rL LLVM

https://reviews.llvm.org/D49836