[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:179
+  ; Ensure the spill is of the full super-reg.
+  call void asm sideeffect "buffer_store_dwordx2 $0, off, s[0:3], s7", "r"(<2 x i32> %a)
+
----------------
This inline assembly is invalid, since it doesn't list the memory or physical register uses. 

You don't need something meaningful here anyway, you should just need a comment with the register name to model the constraint


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Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:210
+  ; Ensure the spill is of the full super-reg.
+  call void asm sideeffect "buffer_store_dwordx2 $0, off, s[0:3], s7", "r"(<2 x i32> %a)
+
----------------
Ditto


https://reviews.llvm.org/D49448