[llvm] r337646 - [mips] Move out the WrapperPat declaration from the NotInMicroMips predicate
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 21 09:16:03 PDT 2018
Author: atanasyan
Date: Sat Jul 21 09:16:03 2018
New Revision: 337646
URL: http://llvm.org/viewvc/llvm-project?rev=337646&view=rev
Log:
[mips] Move out the WrapperPat declaration from the NotInMicroMips predicate
This is a follow-up to the rL335185. Those commit adds some WrapperPat
patterns for microMIPS target. But declaration of the WrapperPat class
is under the NotInMicroMips predicate and microMIPS patterns cannot be
selected because predicate (Subtarget->inMicroMipsMode()) &&
(!Subtarget->inMicroMipsMode()) is always false.
This change move out the WrapperPat class declaration from the
NotInMicroMips predicate and enables microMIPS WrapperPat patterns.
Differential revision: https://reviews.llvm.org/D49533
Added:
llvm/trunk/test/CodeGen/Mips/tglobaladdr-wrapper.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/tls.ll
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=337646&r1=337645&r2=337646&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Sat Jul 21 09:16:03 2018
@@ -3098,6 +3098,10 @@ multiclass MipsHiLoRelocs<Instruction Lu
(Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>;
}
+// wrapper_pic
+class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
+ MipsPat<(MipsWrapper RC:$gp, node:$in), (ADDiuOp RC:$gp, node:$in)>;
+
let AdditionalPredicates = [NotInMicroMips] in {
defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1;
@@ -3111,11 +3115,6 @@ let AdditionalPredicates = [NotInMicroMi
def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
(ADDiu GPR32:$gp, tconstpool:$in)>, ISA_MIPS1, ABI_NOT_N64;
- // wrapper_pic
- class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
- MipsPat<(MipsWrapper RC:$gp, node:$in),
- (ADDiuOp RC:$gp, node:$in)>;
-
def : WrapperPat<tglobaladdr, ADDiu, GPR32>, ISA_MIPS1;
def : WrapperPat<tconstpool, ADDiu, GPR32>, ISA_MIPS1;
def : WrapperPat<texternalsym, ADDiu, GPR32>, ISA_MIPS1;
Added: llvm/trunk/test/CodeGen/Mips/tglobaladdr-wrapper.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tglobaladdr-wrapper.ll?rev=337646&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tglobaladdr-wrapper.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/tglobaladdr-wrapper.ll Sat Jul 21 09:16:03 2018
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic \
+; RUN: < %s 2>&1 | FileCheck %s --check-prefix=32
+; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic -mattr=+micromips \
+; RUN: < %s 2>&1 | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
+; RUN: < %s 2>&1 | FileCheck %s --check-prefix=64
+
+ at x = global i32 0
+ at a = global i32 0
+ at b = global i32 0
+
+define void @foo() {
+; 32-LABEL: foo:
+; 32: # %bb.0: # %entry
+; 32-NEXT: lui $2, %hi(_gp_disp)
+; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-NEXT: addu $1, $2, $25
+; 32-NEXT: lw $2, %got(x)($1)
+; 32-NEXT: lw $3, 0($2)
+; 32-NEXT: addiu $4, $1, %got(b)
+; 32-NEXT: addiu $1, $1, %got(a)
+; 32-NEXT: movz $4, $1, $3
+; 32-NEXT: lw $1, 0($4)
+; 32-NEXT: lw $1, 0($1)
+; 32-NEXT: jr $ra
+; 32-NEXT: sw $1, 0($2)
+;
+; MM-LABEL: foo:
+; MM: # %bb.0: # %entry
+; MM-NEXT: lui $2, %hi(_gp_disp)
+; MM-NEXT: addiu $2, $2, %lo(_gp_disp)
+; MM-NEXT: addu $2, $2, $25
+; MM-NEXT: lw $3, %got(x)($2)
+; MM-NEXT: lw16 $4, 0($3)
+; MM-NEXT: addiu $5, $2, %got(b)
+; MM-NEXT: addiu $1, $2, %got(a)
+; MM-NEXT: movz $5, $1, $4
+; MM-NEXT: lw16 $2, 0($5)
+; MM-NEXT: lw16 $2, 0($2)
+; MM-NEXT: sw16 $2, 0($3)
+; MM-NEXT: jrc $ra
+;
+; 64-LABEL: foo:
+; 64: # %bb.0: # %entry
+; 64-NEXT: lui $1, %hi(%neg(%gp_rel(foo)))
+; 64-NEXT: daddu $1, $1, $25
+; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(foo)))
+; 64-NEXT: ld $2, %got_disp(x)($1)
+; 64-NEXT: lw $3, 0($2)
+; 64-NEXT: daddiu $4, $1, %got_disp(b)
+; 64-NEXT: daddiu $1, $1, %got_disp(a)
+; 64-NEXT: movz $4, $1, $3
+; 64-NEXT: ld $1, 0($4)
+; 64-NEXT: lw $1, 0($1)
+; 64-NEXT: jr $ra
+; 64-NEXT: sw $1, 0($2)
+entry:
+ %0 = load i32, i32* @x, align 4
+ %cmp2 = icmp eq i32 %0, 0
+ %1 = load i32, i32* @a, align 4
+ %2 = load i32, i32* @b, align 4
+ %cond = select i1 %cmp2, i32 %1, i32 %2
+ store i32 %cond, i32* @x, align 4
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=337646&r1=337645&r2=337646&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tls.ll Sat Jul 21 09:16:03 2018
@@ -1,5 +1,7 @@
; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=PIC,CHECK
+; RUN: llc -mtriple=mipsel-- -mattr=+micromips -disable-mips-delay-filler \
+; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=MM,CHECK
; RUN: llc -mtriple=mipsel-- -relocation-model=static -disable-mips-delay-filler < \
; RUN: %s | FileCheck %s -check-prefixes=STATIC,CHECK
; RUN: llc -mtriple=mipsel-- -relocation-model=static -disable-mips-delay-filler \
@@ -20,6 +22,13 @@ entry:
; PIC-DAG: jalr $25
; PIC-DAG: lw $2, 0($2)
+; MM-LABEL: f1:
+; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
+; MM-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
+; MM-DAG: addiu $4, $[[R0]], %tlsgd(t1)
+; MM-DAG: jalr $25
+; MM-DAG: lw16 $2, 0($2)
+
; STATIC-LABEL: f1:
; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
@@ -43,6 +52,13 @@ entry:
; PIC-DAG: jalr $25
; PIC-DAG: lw $2, 0($2)
+; MM-LABEL: f2:
+; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
+; MM-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
+; MM-DAG: addiu $4, $[[R0]], %tlsgd(t2)
+; MM-DAG: jalr $25
+; MM-DAG: lw16 $2, 0($2)
+
; STATICGP-LABEL: f2:
; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
@@ -69,6 +85,12 @@ entry:
; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2
; PIC: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
+; MM: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
+; MM: jalr $25
+; MM: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
+; MM: addu16 $[[R1:[0-9]+]], $[[R0]], $2
+; MM: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
+
%0 = load i32, i32* @f3.i, align 4
%inc = add nsw i32 %0, 1
store i32 %inc, i32* @f3.i, align 4
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