[PATCH] D46179: [X86] Lowering adds/addus/subs/subus intrinsics to native IR (LLVM part)

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:36873
+      for (unsigned i = 0; i < NumOperands; ++i) {
+        APInt Elt = cast<ConstantSDNode>(Op.getOperand(i))->getAPIntValue();
+        if ((Signed && Elt.isSignedIntN(EltSize)) ||
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isBuildVectorConstantSDNodes allows undef elements which will fail this cast. You need to add a skip for undef. Please add test cases.


Repository:
  rL LLVM

https://reviews.llvm.org/D46179