[PATCH] D49562: [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: efriedma, craig.topper, spatel.

As was done for vector rotations, we can efficiently use ISD::MULHU for vXi8/vXi16 ISD::SRL lowering (unless we have AVX512 which do this more efficiently through ext+shift+trunc).

Shift-by-zero cases are still problematic (mainly on v32i8 due to extra AND/ANDN/OR or VPBLENDVB blend masks but v8i16/v16i16 aren't great either if PBLENDW fails) so I've limited this first patch to known non-zero cases.


Repository:
  rL LLVM

https://reviews.llvm.org/D49562

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/combine-shl.ll
  test/CodeGen/X86/vector-shift-lshr-256.ll

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