[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D49448#1168395, @scott.linder wrote:

> Address some more feedback; use `-stress-regalloc` to cut down on the clobbers needed, add non-kernel tests, explicitly test the increment/decrement case, including the scratch offset SGPR.
>
> I will try adding a MIR test to exercise the subregister condition and loop; with an IR test I don't know how to get a VGPR with subregs to survive "AMDGPU DAG->DAG Pattern Instruction Selection"


A physical register tuple inline asm use should work


https://reviews.llvm.org/D49448