[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

There's a shift uop in the BTR/BTS/BTC memory flow so thats port06 restricted. And the bit test uop should also be port 06 restricted just like the register form.


https://reviews.llvm.org/D49243