[PATCH] D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 156053.
andreadb added a comment.

Patch updated.

Tablegen changes related to the new "invalid register operand" checker are no longer part of this patch. Those changes have been committed at r337378.

Scheduling predicates that are common to all X86 subtargets have been moved to a separate .td file named X86SchedPredicates.td.
This chage is motivated by the fact that `CheckOpcode` predicates require that tablegen instruction definitions are already visible/accessible. That means, file X86SchedPredicates.td has to be included after the `#include X86InstrInfo.td` in X86.td.

The auto-generated definition of `isThreeOperandsLEA()`  now looks like this:

  static bool isThreeOperandsLEA(const MachineInstr &MI) {
    return (
      (
        MI.getOpcode() == X86::LEA32r
        || MI.getOpcode() == X86::LEA64r
        || MI.getOpcode() == X86::LEA64_32r
        || MI.getOpcode() == X86::LEA16r
      )
      && MI.getOperand(1).isReg()
      && MI.getOperand(1).getReg() != 0
      && MI.getOperand(3).isReg()
      && MI.getOperand(3).getReg() != 0
      && (
        (
          MI.getOperand(4).isImm()
          && MI.getOperand(4).getImm() != 0
        )
        || (MI.getOperand(4).isGlobal())
      )
    );
  }


https://reviews.llvm.org/D49436

Files:
  lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
  lib/Target/X86/X86.td
  lib/Target/X86/X86FixupLEAs.cpp
  lib/Target/X86/X86SchedPredicates.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86ScheduleBtVer2.td
  test/CodeGen/X86/lea32-schedule.ll
  test/CodeGen/X86/lea64-schedule.ll
  test/CodeGen/X86/mul-constant-i32.ll
  test/CodeGen/X86/mul-constant-i64.ll
  test/CodeGen/X86/schedule-x86-64-shld.ll
  test/tools/llvm-mca/X86/BtVer2/resources-lea.s

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