[PATCH] D46179: [X86] Lowering adds/addus/subs/subus intrinsics to native IR (LLVM part)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:36289
+        APInt Elt = cast<ConstantSDNode>(Op.getOperand(i))->getAPIntValue();
+        Elt = Elt.getHiBits(Elt.isSignedIntN(ExtEltSize) ? ExtPartSize + 1
+                                                         : ExtPartSize);
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Why can't you just use APInt::isIntN for unsigned and APInt::isSignedIntN for signed? Why do you need to extract the high bits yourself?


Repository:
  rL LLVM

https://reviews.llvm.org/D46179