[PATCH] D49393: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on partially written registers.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: andreadb, courbet, RKSimon, craig.topper, GGanesh.
Herald added a subscriber: gbedwell.

Pretty mechanical follow-up for https://reviews.llvm.org/D49196.

As microarchitecture.pdf notes, "20 AMD Ryzen pipeline", 
"20.8 Register renaming and out-of-order schedulers":

  The integer register file has 168 physical registers of 64 bits each.
  The floating point register file has 160 registers of 128 bits each.

"20.14 Partial register access":

  The processor always keeps the different parts of an integer register together. 
  ...
  An instruction that writes to part of a register will therefore have a false dependence
  on any previous write to the same register or any part of it.

There is one caveat, however:

  An instruction that writes to a 32-bit register will not have any false dependence on the
  corresponding 64-bit register because the upper part of the 64-bit register is set to zero.

I have added a test (`partial-reg-update-7.s`), but something seems to be missing,
if i keep `GR32` in `RegisterFile<>`, the test doesn't change.


Repository:
  rL LLVM

https://reviews.llvm.org/D49393

Files:
  lib/Target/X86/X86ScheduleZnver1.td
  test/tools/llvm-mca/X86/Znver1/partial-reg-update-2.s
  test/tools/llvm-mca/X86/Znver1/partial-reg-update-3.s
  test/tools/llvm-mca/X86/Znver1/partial-reg-update-4.s
  test/tools/llvm-mca/X86/Znver1/partial-reg-update-5.s
  test/tools/llvm-mca/X86/Znver1/partial-reg-update-6.s

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