[PATCH] D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td:56
 // Reference: www.realworldtech.com/jaguar/4/
 def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>;
 
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andreadb wrote:
> lebedev.ri wrote:
> > A bit late, but i'm not sure about the FP registers.
> > ```
> > But the high and low 64 bits of a 128 bit register are treated as independent on
> > Bobcat, and the high and low 128 bits of a 256 bit register are treated as independent on
> > Jaguar.
> > ```
> > Does that mean that it should be `def JFpuPRF: RegisterFile<72, [VR128, VR256], [1, 1, 2]>;` ?
> > Or does that mean `on Bobcat <and later>`?
> Register class VR64 is the class used by x87/mmx registers.
> Those eight registers don't alias with XMM/YMM registers, and they are subject to register renaming.
> 
> Bobcat provides native support for 64-bit data types, but not 128-bit data types. So, operations on 128-bit data types are split into 2x64-bit pairs. Internally, the PRF consumes two physical registers to map a single XMM write. 
> 
> Agner describes this in Section 21.1: `The Bobcat has 64-bit physical registers and uses two such registers to save a 128-bit vector.`
> 
> I hope it helps.
> -Andrea
Thank you.
Yes, i think it did.
Basically, i think it confirmed that the FP `RegisterFile` for both the btver2, and znver1 is correct.
So i just need to adjust the integer `RegisterFile` on znver1.


Repository:
  rL LLVM

https://reviews.llvm.org/D49196