[PATCH] D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: include/llvm/Target/TargetSchedule.td:465-466
+//
+// This implementation assumes that there is no limit in the number of renames
+// per cycle. Also, there is no limit to how many times the same logical
+// register can be renamed during the same cycle.
----------------
This should probably be a TODO.
"Software Optimization Guide for AMD Family 17h Processors"
http://developer.amd.com/wordpress/media/2013/12/55723_SOG_Fam_17h_Processors_3.00.pdf
"34 Microarchitecture of AMD Family 17h Processor Chapter 2"
"2.11 Floating-Point Unit"
   It can handle dispatch and renaming of 4 floating point micro ops per cycle

So maybe having one single `DispatchWidth` per `ProcResGroup` and using that for
both the dispatch and renaming is the way to go.


https://reviews.llvm.org/D49196