[llvm] r337078 - [x86/SLH] Add an assert to catch if we ever end up trying to harden

[Chandler Carruth via llvm-commits]

Author: chandlerc
Date: Fri Jul 13 17:52:09 2018
New Revision: 337078

URL: http://llvm.org/viewvc/llvm-project?rev=337078&view=rev
Log:
[x86/SLH] Add an assert to catch if we ever end up trying to harden
post-load a register that isn't valid for use with OR or SHRX.

Modified:
    llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp

Modified: llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp?rev=337078&r1=337077&r2=337078&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp Fri Jul 13 17:52:09 2018
@@ -1533,6 +1533,14 @@ void X86SpeculativeLoadHardeningPass::ha
   unsigned OrOpCodes[] = {X86::OR8rr, X86::OR16rr, X86::OR32rr, X86::OR64rr};
   unsigned OrOpCode = OrOpCodes[Log2_32(DefRegBytes)];
 
+#ifndef NDEBUG
+  const TargetRegisterClass *OrRegClasses[] = {
+      &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,
+      &X86::GR64RegClass};
+  assert(DefRC->hasSuperClassEq(OrRegClasses[Log2_32(DefRegBytes)]) &&
+         "Cannot define this register with OR instruction!");
+#endif
+
   unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit};
 
   auto GetStateRegInRC = [&](const TargetRegisterClass &RC) {