[PATCH] D49312: [X86][SLH] Regroup the instructions in isDataInvariantLoad a little. NFC

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added a reviewer: chandlerc.

-Move BSF/BSR to the same group as TZCNT/LZCNT/POPCNT.
-Split some of the bit manipulation instructions away from TZCNT/LZCNT/POPCNT. These are things like 'x & (x - 1)' which are composed of a few simple arithmetic operations. These aren't nearly as complicated/surprising as counting bits.
-Move BEXTR/BZHI into their own group. They aren't like a simple arithmethic op or the bit manipulation instructions. They're more like a shift+and.


https://reviews.llvm.org/D49312

Files:
  lib/Target/X86/X86SpeculativeLoadHardening.cpp

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