[llvm] r336979 - [AArch64][SVE] Asm: Support for insert element (INSR) instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 13 01:51:57 PDT 2018
Author: s.desmalen
Date: Fri Jul 13 01:51:57 2018
New Revision: 336979
URL: http://llvm.org/viewvc/llvm-project?rev=336979&view=rev
Log:
[AArch64][SVE] Asm: Support for insert element (INSR) instructions.
Insert general purpose register into shifted vector, e.g.
insr z0.s, w0
insr z0.d, x0
Insert SIMD&FP scalar register into shifted vector, e.g.
insr z0.b, b0
insr z0.h, h0
insr z0.s, s0
insr z0.d, d0
Added:
llvm/trunk/test/MC/AArch64/SVE/insr-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/insr.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=336979&r1=336978&r2=336979&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Fri Jul 13 01:51:57 2018
@@ -113,6 +113,8 @@ let Predicates = [HasSVE] in {
defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
+ defm INSR_ZR : sve_int_perm_insrs<"insr">;
+ defm INSR_ZV : sve_int_perm_insrv<"insr">;
def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=336979&r1=336978&r2=336979&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Fri Jul 13 01:51:57 2018
@@ -658,6 +658,55 @@ multiclass sve_int_perm_tbl<string asm>
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
}
+class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty,
+ RegisterClass srcRegType>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
+ asm, "\t$Zdn, $Rm",
+ "",
+ []>, Sched<[]> {
+ bits<5> Rm;
+ bits<5> Zdn;
+ let Inst{31-24} = 0b00000101;
+ let Inst{23-22} = sz8_64;
+ let Inst{21-10} = 0b100100001110;
+ let Inst{9-5} = Rm;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_perm_insrs<string asm> {
+ def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
+ def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
+ def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
+ def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
+}
+
+class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
+ RegisterClass srcRegType>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
+ asm, "\t$Zdn, $Vm",
+ "",
+ []>, Sched<[]> {
+ bits<5> Vm;
+ bits<5> Zdn;
+ let Inst{31-24} = 0b00000101;
+ let Inst{23-22} = sz8_64;
+ let Inst{21-10} = 0b110100001110;
+ let Inst{9-5} = Vm;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_perm_insrv<string asm> {
+ def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
+ def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
+ def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
+ def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
+}
+
+
//===----------------------------------------------------------------------===//
// SVE Vector Select Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE/insr-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/insr-diagnostics.s?rev=336979&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/insr-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/insr-diagnostics.s Fri Jul 13 01:51:57 2018
@@ -0,0 +1,45 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid scalar operand size.
+
+insr z31.b, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.b, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.h, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.h, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.s, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.s, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.d, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.d, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.b, h0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.b, h0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.h, s0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.h, s0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.s, d0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.s, d0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr z31.d, b0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr z31.d, b0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/insr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/insr.s?rev=336979&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/insr.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/insr.s Fri Jul 13 01:51:57 2018
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+insr z0.b, w0
+// CHECK-INST: insr z0.b, w0
+// CHECK-ENCODING: [0x00,0x38,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 24 05 <unknown>
+
+insr z0.h, w0
+// CHECK-INST: insr z0.h, w0
+// CHECK-ENCODING: [0x00,0x38,0x64,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 64 05 <unknown>
+
+insr z0.s, w0
+// CHECK-INST: insr z0.s, w0
+// CHECK-ENCODING: [0x00,0x38,0xa4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 a4 05 <unknown>
+
+insr z0.d, x0
+// CHECK-INST: insr z0.d, x0
+// CHECK-ENCODING: [0x00,0x38,0xe4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 e4 05 <unknown>
+
+insr z31.b, wzr
+// CHECK-INST: insr z31.b, wzr
+// CHECK-ENCODING: [0xff,0x3b,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 24 05 <unknown>
+
+insr z31.h, wzr
+// CHECK-INST: insr z31.h, wzr
+// CHECK-ENCODING: [0xff,0x3b,0x64,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 64 05 <unknown>
+
+insr z31.s, wzr
+// CHECK-INST: insr z31.s, wzr
+// CHECK-ENCODING: [0xff,0x3b,0xa4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b a4 05 <unknown>
+
+insr z31.d, xzr
+// CHECK-INST: insr z31.d, xzr
+// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
+
+insr z31.b, b31
+// CHECK-INST: insr z31.b, b31
+// CHECK-ENCODING: [0xff,0x3b,0x34,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 34 05 <unknown>
+
+insr z31.h, h31
+// CHECK-INST: insr z31.h, h31
+// CHECK-ENCODING: [0xff,0x3b,0x74,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 74 05 <unknown>
+
+insr z31.s, s31
+// CHECK-INST: insr z31.s, s31
+// CHECK-ENCODING: [0xff,0x3b,0xb4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b b4 05 <unknown>
+
+insr z31.d, d31
+// CHECK-INST: insr z31.d, d31
+// CHECK-ENCODING: [0xff,0x3b,0xf4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b f4 05 <unknown>
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