[PATCH] D49194: [WebAssembly] Add tests for weaker memory consistency orderings

[Heejin Ahn via Phabricator via llvm-commits]

aheejin added a comment.

Currently LLVM treats all atomic IR instructions as volatile. Link0 <https://github.com/llvm-mirror/llvm/blob/d79789afc64bdd2ef879c97f97848f436bf0692d/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L6035-L6039> Link1 <https://github.com/llvm-mirror/llvm/blob/d79789afc64bdd2ef879c97f97848f436bf0692d/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L6000-L6003> So I'm not exactly sure what you mean by 'upgrade `volatile` to `seq_cst`' is. For non-atomic volatile memory instructions, they are not atomic, so they don't have orderings.

And I haven't implemented translation rules for `fence` or `asm volatile(""::: "memory");` yet. The wasm thread proposal <https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md> does not have a fence instruction itself. Because in the current wasm spec all atomic memory accesses are sequentially consistent, do you think we can translate them to a nop safely? Please let me know if I'm mistaken.

Thank you!


Repository:
  rL LLVM

https://reviews.llvm.org/D49194