[PATCH] D49262: [DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/AArch64/aarch64-be-bv.ll:33
-  ; CHECK-NEXT:    movi	   v[[REG2:[0-9]+]].4s, #1, lsl #16
-  ; CHECK-NEXT:    add	   v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
   ; CHECK-NEXT:    umov	   w{{[0-9]+}}, v[[REG1]].h[0]
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efriedma wrote:
> This is nice, but it's destroying the intent of the test, which is to check that we generate the correct movi instruction.
Am I missing something - why the extractelement - why not return the <8 x i16> add result directly?


Repository:
  rL LLVM

https://reviews.llvm.org/D49262