[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon requested changes to this revision.
RKSimon added inline comments.
This revision now requires changes to proceed.


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Comment at: lib/Target/X86/X86InstrInfo.td:1799
 // other operand is in a register. When it's an immediate, bt is still fast.
 let SchedRW = [WriteALU] in {
 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
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Why isn't this WriteBTLd ?


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Comment at: lib/Target/X86/X86Schedule.td:122
+// Bit Test
+defm WriteBTr    : X86SchedWritePair;
+
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lebedev.ri wrote:
> Hmm. Nits:
> 1. (not a nit) The suffix `r` notes that only the non-mem versions are covered.
>    I wonder if we can convey that somehow better.
> 2. These cover 4 different bit-test instructions - `bt`,`bt[rcs]`
>    Naming this `WriteBTr` //may// be confizing - is this only about `bt` instruction?
>    How about calling it `WriteBitTest`?
I'm confused - this should be probably be called WriteBT. But then you've declared this as a X86SchedWritePair but you're not using the folded half of the pair?


https://reviews.llvm.org/D49243