[llvm] r336889 - [X86] Remove i128 type from FR128 regclass.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Jul 12 00:30:01 2018
New Revision: 336889

URL: http://llvm.org/viewvc/llvm-project?rev=336889&view=rev
Log:
[X86] Remove i128 type from FR128 regclass.

i128 isn't a legal type in our x86 implementation today. So remove this and the few patterns that used it until it becomes necessary.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336889&r1=336888&r2=336889&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul 12 00:30:01 2018
@@ -8117,11 +8117,6 @@ def : Pat<(X86fand FR128:$src1, FR128:$s
            (ANDPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
                     (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
 
-def : Pat<(and FR128:$src1, FR128:$src2),
-          (COPY_TO_REGCLASS
-           (ANDPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
-                    (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
-
 def : Pat<(X86for FR128:$src1, (memopf128 addr:$src2)),
           (COPY_TO_REGCLASS
            (ORPSrm (COPY_TO_REGCLASS FR128:$src1, VR128), f128mem:$src2),
@@ -8132,11 +8127,6 @@ def : Pat<(X86for FR128:$src1, FR128:$sr
            (ORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
                    (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
 
-def : Pat<(or FR128:$src1, FR128:$src2),
-          (COPY_TO_REGCLASS
-           (ORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
-                   (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
-
 def : Pat<(X86fxor FR128:$src1, (memopf128 addr:$src2)),
           (COPY_TO_REGCLASS
            (XORPSrm (COPY_TO_REGCLASS FR128:$src1, VR128), f128mem:$src2),
@@ -8146,11 +8136,6 @@ def : Pat<(X86fxor FR128:$src1, FR128:$s
           (COPY_TO_REGCLASS
            (XORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
                     (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
-
-def : Pat<(xor FR128:$src1, FR128:$src2),
-          (COPY_TO_REGCLASS
-           (XORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
-                    (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
 
 //===----------------------------------------------------------------------===//
 // GFNI instructions

Modified: llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td?rev=336889&r1=336888&r2=336889&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td Thu Jul 12 00:30:01 2018
@@ -48,8 +48,6 @@ def : Pat<(v2f64 (bitconvert (v4i32 VR12
 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
-def : Pat<(f128  (bitconvert (i128  FR128:$src))), (f128  FR128:$src)>;
-def : Pat<(i128  (bitconvert (f128  FR128:$src))), (i128  FR128:$src)>;
 
 // Bitcasts between 256-bit vector types. Return the original type since
 // no instruction is needed for the conversion

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=336889&r1=336888&r2=336889&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Jul 12 00:30:01 2018
@@ -504,7 +504,7 @@ def FR32 : RegisterClass<"X86", [f32], 3
 
 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
 
-def FR128 : RegisterClass<"X86", [i128, f128], 128, (add FR32)>;
+def FR128 : RegisterClass<"X86", [f128], 128, (add FR32)>;
 
 
 // FIXME: This sets up the floating point register files as though they are f64