[llvm] r336728 - [X86] Remove X86ISD::MOVLPS and X86ISD::MOVLPD. NFCI
Mikael Holmén via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 11 22:45:05 PDT 2018
Thanks!
/Mikael
On 07/11/2018 03:46 PM, Andrea Di Biagio wrote:
> I have just uploaded the full patch for review here:
> https://reviews.llvm.org/D49182
>
>
> On Wed, Jul 11, 2018 at 1:19 PM, Mikael Holmén
> <mikael.holmen at ericsson.com <mailto:mikael.holmen at ericsson.com>> wrote:
>
> Hi,
>
> Indeed, with that patch "my" case doesn't hit the assertion anymore
> either.
>
> Thanks,
> Mikael
>
>
> On 07/11/2018 02:03 PM, Andrea Di Biagio wrote:
>
> For the record.
> The instructions affected by the missing `mayLoad` flag are:
> MOVLPSrm
> VMOVLPSrm
> VMOVLPSZ128rm
>
> The diff below would fix the issue with the (V)MOVLPSrm.
>
> Index: lib/Target/X86/X86InstrSSE.td
> ===================================================================
> --- lib/Target/X86/X86InstrSSE.td (revision 336790)
> +++ lib/Target/X86/X86InstrSSE.td (working copy)
> @@ -650,14 +650,17 @@
>
> multiclass sse12_mov_hilo_packed<bits<8>opc,
> SDPatternOperator psnode,
> SDPatternOperator pdnode, string base_opc> {
> - let Predicates = [UseAVX] in
> +
> + let mayLoad = 1 in {
> + let Predicates = [UseAVX] in
> defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode,
> pdnode, base_opc,
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
> VEX_4V, VEX_WIG;
>
> - let Constraints = "$src1 = $dst" in
> + let Constraints = "$src1 = $dst" in
> defm NAME : sse12_mov_hilo_packed_base<opc, psnode,
> pdnode, base_opc,
> "\t{$src2, $dst|$dst, $src2}">;
> + }
> }
>
> defm MOVL : sse12_mov_hilo_packed<0x12, null_frag, null_frag,
> "movlp">;
>
> On Wed, Jul 11, 2018 at 12:34 PM, Andrea Di Biagio
> <andrea.dibiagio at gmail.com <mailto:andrea.dibiagio at gmail.com>
> <mailto:andrea.dibiagio at gmail.com
> <mailto:andrea.dibiagio at gmail.com>>> wrote:
>
> I found a similar issue.
>
>
> Before 336728, the "mayLoad" flag for the (V)MOVLPSrm was
> automatically inferred (in
> utils/Tablegen/CodeGenDAGPatterns.cpp)
> directly from the default pattern associated with the
> instruction
> definition.
>
> With 336728, `X86Movlps` is gone. However, the instruction
> definition in tablegen leaves the "mayLoad" flag unset for the
> (V)MOVLPSrm.
> Later on, CodeGenDAGPatterns::InferInstructionFlags() sees that
> (V)MOVLPSrm has undefined flags and no pattern. So, it
> conservatively sets the "hasSideEffects" flag to true.
>
> The assert is probably a consequence of all of this:
>
> there is no 'mayLoad' associated with (V)MOVLPSrm, however,
> VMOVLPSrm is used as the variant to use with a folded
> memory operand.
>
>
> On Wed, Jul 11, 2018 at 12:04 PM, Mikael Holmén via
> llvm-commits
> <llvm-commits at lists.llvm.org
> <mailto:llvm-commits at lists.llvm.org>
> <mailto:llvm-commits at lists.llvm.org
> <mailto:llvm-commits at lists.llvm.org>>>
>
> wrote:
>
> Hi Craig,
>
> The following (llvm-stress generated and bugpoint
> reduced) case
> starts to crash the register allocator with this patch:
>
> llc -march=x86-64 -mcpu=corei7 -o /dev/null fold.ll
>
> gives
>
> llc: ../lib/CodeGen/TargetInstrInfo.cpp:594:
> llvm::MachineInstr
>
> *llvm::TargetInstrInfo::foldMemoryOperand(llvm::MachineInstr &,
> ArrayRef<unsigned int>, int, llvm::LiveIntervals *) const:
> Assertion `(!(Flags & MachineMemOperand::MOLoad) ||
> NewMI->mayLoad()) && "Folded a use to a non-load!"' failed.
> Stack dump:
> 0. Program arguments: build-all/bin/llc -march=x86-64
> -mcpu=corei7 -o /dev/null fold.ll
> 1. Running pass 'Function Pass Manager' on module
> 'fold.ll'.
> 2. Running pass 'Greedy Register Allocator' on
> function
> '@autogen_SD17302'
> #0 0x0000000001ff28f4 PrintStackTraceSignalHandler(void*)
> (build-all/bin/llc+0x1ff28f4)
> #1 0x0000000001ff0b60 llvm::sys::RunSignalHandlers()
> (build-all/bin/llc+0x1ff0b60)
> #2 0x0000000001ff2c58 SignalHandler(int)
> (build-all/bin/llc+0x1ff2c58)
> #3 0x00007f7b62559330 __restore_rt
> (/lib/x86_64-linux-gnu/libpthread.so.0+0x10330)
> #4 0x00007f7b61148c37 gsignal
>
> /build/eglibc-ripdx6/eglibc-2.19/signal/../nptl/sysdeps/unix/sysv/linux/raise.c:56:0
> #5 0x00007f7b6114c028 abort
> /build/eglibc-ripdx6/eglibc-2.19/stdlib/abort.c:91:0
> #6 0x00007f7b61141bf6 __assert_fail_base
> /build/eglibc-ripdx6/eglibc-2.19/assert/assert.c:92:0
> #7 0x00007f7b61141ca2
> (/lib/x86_64-linux-gnu/libc.so.6+0x2fca2)
> #8 0x000000000188be0d
>
> llvm::TargetInstrInfo::foldMemoryOperand(llvm::MachineInstr&,
> llvm::ArrayRef<unsigned int>, int,
> llvm::LiveIntervals*) const
> (build-all/bin/llc+0x188be0d)
> #9 0x00000000018e6607 (anonymous
>
> namespace)::InlineSpiller::foldMemoryOperand(llvm::ArrayRef<std::pair<llvm::MachineInstr*,
> unsigned int> >, llvm::MachineInstr*)
> (build-all/bin/llc+0x18e6607)
> #10 0x00000000018decc5 (anonymous
> namespace)::InlineSpiller::spill(llvm::LiveRangeEdit&)
> (build-all/bin/llc+0x18decc5)
> #11 0x00000000017eb5d9 (anonymous
>
> namespace)::RAGreedy::selectOrSplitImpl(llvm::LiveInterval&,
> llvm::SmallVectorImpl<unsigned int>&,
> llvm::SmallSet<unsigned
> int, 16u, std::less<unsigned int> >&, unsigned int)
> (build-all/bin/llc+0x17eb5d9)
> #12 0x00000000017ea1aa (anonymous
> namespace)::RAGreedy::selectOrSplit(llvm::LiveInterval&,
> llvm::SmallVectorImpl<unsigned int>&)
> (build-all/bin/llc+0x17ea1aa)
> #13 0x000000000190ab1a
> llvm::RegAllocBase::allocatePhysRegs()
> (build-all/bin/llc+0x190ab1a)
> #14 0x00000000017e8ed1 (anonymous
>
> namespace)::RAGreedy::runOnMachineFunction(llvm::MachineFunction&)
> (build-all/bin/llc+0x17e8ed1)
> #15 0x0000000001713749
> llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
> (build-all/bin/llc+0x1713749)
> #16 0x0000000001a3cc7a
> llvm::FPPassManager::runOnFunction(llvm::Function&)
> (build-all/bin/llc+0x1a3cc7a)
> #17 0x0000000001a3ced8
> llvm::FPPassManager::runOnModule(llvm::Module&)
> (build-all/bin/llc+0x1a3ced8)
> #18 0x0000000001a3d40d
> llvm::legacy::PassManagerImpl::run(llvm::Module&)
> (build-all/bin/llc+0x1a3d40d)
> #19 0x00000000006fccb9 compileModule(char**,
> llvm::LLVMContext&)
> (build-all/bin/llc+0x6fccb9)
> #20 0x00000000006fa2b0 main (build-all/bin/llc+0x6fa2b0)
> #21 0x00007f7b61133f45 __libc_start_main
> /build/eglibc-ripdx6/eglibc-2.19/csu/libc-start.c:321:0
> #22 0x00000000006f7b0a _start (build-all/bin/llc+0x6f7b0a)
> Abort
>
> NewMI is
>
> %26:vr128 = MOVLPSrm %26:vr128, %stack.1, 1, $noreg,
> 8, $noreg
>
> when it crashes.
>
> Regards,
> Mikael
>
>
> On 07/10/2018 11:00 PM, Craig Topper via llvm-commits
> wrote:
>
> Author: ctopper
> Date: Tue Jul 10 14:00:22 2018
> New Revision: 336728
>
> URL:
> http://llvm.org/viewvc/llvm-project?rev=336728&view=rev
> <http://llvm.org/viewvc/llvm-project?rev=336728&view=rev>
>
> <http://llvm.org/viewvc/llvm-project?rev=336728&view=rev
> <http://llvm.org/viewvc/llvm-project?rev=336728&view=rev>>
> Log:
> [X86] Remove X86ISD::MOVLPS and X86ISD::MOVLPD. NFCI
>
> These ISD nodes try to select the MOVLPS and MOVLPD
> instructions which are special load only
> instructions. They
> load data and merge it into the lower 64-bits of an XMM
> register. They are logically equivalent to our
> MOVSD node
> plus a load.
>
> There was only one place in X86ISelLowering that
> used MOVLPD
> and no places that selected MOVLPS. The one place that
> selected MOVLPD had to choose between it and MOVSD
> based on
> whether there was a load. But lowering is too early
> to tell
> if the load can really be folded. So in isel we have
> patterns that use MOVSD for MOVLPD if we can't find
> a load.
>
> We also had patterns that select the MOVLPD
> instruction for
> a MOVSD if we can find a load, but didn't choose
> the MOVLPD
> ISD opcode for some reason.
>
> So it seems better to just standardize on MOVSD ISD
> opcode
> and manage MOVSD vs MOVLPD instruction with isel
> patterns.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/X86/X86InstrAVX512.td
>
> llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336728&r1=336727&r2=336728&view=diff>
>
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336728&r1=336727&r2=336728&view=diff>>
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> Tue Jul 10
> 14:00:22 2018
> @@ -4369,8 +4369,6 @@ static bool
> isTargetShuffle(unsigned Opc
> case X86ISD::VSRLDQ:
> case X86ISD::MOVLHPS:
> case X86ISD::MOVHLPS:
> - case X86ISD::MOVLPS:
> - case X86ISD::MOVLPD:
> case X86ISD::MOVSHDUP:
> case X86ISD::MOVSLDUP:
> case X86ISD::MOVDDUP:
> @@ -5951,10 +5949,6 @@ static bool
> getTargetShuffleMask(SDNode
> DecodeMOVDDUPMask(NumElems, Mask);
> IsUnary = true;
> break;
> - case X86ISD::MOVLPD:
> - case X86ISD::MOVLPS:
> - // Not yet implemented
> - return false;
> case X86ISD::VPERMIL2: {
> assert(N->getOperand(0).getValueType() == VT &&
> "Unexpected value type");
> assert(N->getOperand(1).getValueType() == VT &&
> "Unexpected value type");
> @@ -11363,8 +11357,7 @@ static SDValue
> lowerV2F64VectorShuffle(c
> // We can either use a special instruction
> to load
> over the low double or
> // to move just the low double.
> return DAG.getNode(
> - isShuffleFoldableLoad(V1S) ?
> X86ISD::MOVLPD :
> X86ISD::MOVSD,
> - DL, MVT::v2f64, V2,
> + X86ISD::MOVSD, DL, MVT::v2f64, V2,
> DAG.getNode(ISD::SCALAR_TO_VECTOR, DL,
> MVT::v2f64, V1S));
> if (Subtarget.hasSSE41())
> @@ -26041,8 +26034,6 @@ const char
> *X86TargetLowering::getTarget
> case X86ISD::SHUF128: return
> "X86ISD::SHUF128";
> case X86ISD::MOVLHPS: return
> "X86ISD::MOVLHPS";
> case X86ISD::MOVHLPS: return
> "X86ISD::MOVHLPS";
> - case X86ISD::MOVLPS: return
> "X86ISD::MOVLPS";
> - case X86ISD::MOVLPD: return
> "X86ISD::MOVLPD";
> case X86ISD::MOVDDUP: return
> "X86ISD::MOVDDUP";
> case X86ISD::MOVSHDUP: return
> "X86ISD::MOVSHDUP";
> case X86ISD::MOVSLDUP: return
> "X86ISD::MOVSLDUP";
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336728&r1=336727&r2=336728&view=diff>
>
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336728&r1=336727&r2=336728&view=diff>>
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h
> (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue
> Jul 10
> 14:00:22 2018
> @@ -408,8 +408,6 @@ namespace llvm {
> MOVSLDUP,
> MOVLHPS,
> MOVHLPS,
> - MOVLPS,
> - MOVLPD,
> MOVSD,
> MOVSS,
> UNPCKL,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336728&r1=336727&r2=336728&view=diff>
>
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336728&r1=336727&r2=336728&view=diff>>
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td
> (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue
> Jul 10
> 14:00:22 2018
> @@ -4439,11 +4439,6 @@ let Predicates = [HasAVX512]
> in {
> def : Pat<(v2f64 (X86Movsd VR128X:$src1,
> (scalar_to_vector FR64X:$src2))),
> (VMOVSDZrr VR128X:$src1,
> (COPY_TO_REGCLASS
> FR64X:$src2, VR128X))>;
> -
> - def : Pat<(v2f64 (X86Movlpd VR128X:$src1,
> VR128X:$src2)),
> - (VMOVSDZrr VR128X:$src1, VR128X:$src2)>;
> - def : Pat<(v4f32 (X86Movlps VR128X:$src1,
> VR128X:$src2)),
> - (VMOVSDZrr VR128X:$src1, VR128X:$src2)>;
> }
> let ExeDomain = SSEPackedInt, SchedRW =
> [SchedWriteVecLogic.XMM] in {
> @@ -6405,7 +6400,8 @@ def VMOVHLPSZrr :
> AVX512PSI<0x12, MRMSrc
> // All patterns was taken from SSS implementation.
>
> //===----------------------------------------------------------------------===//
> -multiclass avx512_mov_hilo_packed<bits<8> opc,
> string
> OpcodeStr, SDNode OpNode,
> +multiclass avx512_mov_hilo_packed<bits<8> opc, string
> OpcodeStr,
> +
> SDPatternOperator OpNode,
>
> X86VectorVTInfo _> {
> let ExeDomain = _.ExeDomain in
> def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
> @@ -6423,9 +6419,9 @@ defm VMOVHPSZ128 :
> avx512_mov_hilo_packe
> v4f32x_info>,
> EVEX_CD8<32, CD8VT2>, PS;
> defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16,
> "vmovhpd", X86Unpckl,
> v2f64x_info>,
> EVEX_CD8<64, CD8VT1>, PD, VEX_W;
> -defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12,
> "vmovlps",
> X86Movlps,
> +defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12,
> "vmovlps",
> null_frag,
> v4f32x_info>,
> EVEX_CD8<32, CD8VT2>, PS;
> -defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12,
> "vmovlpd",
> X86Movlpd,
> +defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12,
> "vmovlpd",
> null_frag,
> v2f64x_info>,
> EVEX_CD8<64, CD8VT1>, PD, VEX_W;
> let Predicates = [HasAVX512] in {
> @@ -6440,12 +6436,7 @@ let Predicates = [HasAVX512]
> in {
> def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
> (bc_v2f64 (v2i64
> (scalar_to_vector
> (loadi64 addr:$src2)))))),
> (VMOVHPDZ128rm VR128X:$src1,
> addr:$src2)>;
> - // VMOVLPS patterns
> - def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load
> addr:$src2))),
> - (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
> // VMOVLPD patterns
> - def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load
> addr:$src2))),
> - (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
> def : Pat<(v2f64 (X86Movsd VR128X:$src1,
> (v2f64 (scalar_to_vector
> (loadf64 addr:$src2))))),
> (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
> @@ -6487,14 +6478,6 @@ let Predicates = [HasAVX512]
> in {
> (v2f64 (X86VPermilpi
> VR128X:$src, (i8 1))),
> (iPTR 0))), addr:$dst),
> (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
> - // VMOVLPS patterns
> - def : Pat<(store (v4f32 (X86Movlps (load
> addr:$src1),
> VR128X:$src2)),
> - addr:$src1),
> - (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
> - // VMOVLPD patterns
> - def : Pat<(store (v2f64 (X86Movlpd (load
> addr:$src1),
> VR128X:$src2)),
> - addr:$src1),
> - (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
> }
>
> //===----------------------------------------------------------------------===//
> // FMA - Fused Multiply Operations
>
> Modified:
> llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336728&r1=336727&r2=336728&view=diff>
>
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336728&r1=336727&r2=336728&view=diff>>
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> (original)
> +++
> llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue
> Jul 10 14:00:22 2018
> @@ -374,9 +374,6 @@ def X86Movss :
> SDNode<"X86ISD::MOVSS", S
> def X86Movlhps : SDNode<"X86ISD::MOVLHPS",
> SDTShuff2Op>;
> def X86Movhlps : SDNode<"X86ISD::MOVHLPS",
> SDTShuff2Op>;
> -def X86Movlps : SDNode<"X86ISD::MOVLPS",
> SDTShuff2Op>;
> -def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
> -
> def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>,
> SDTCisInt<0>,
> SDTCisVec<1>,
> SDTCisInt<1>,
>
> SDTCisSameSizeAs<0,1>,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336728&r1=336727&r2=336728&view=diff>
>
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336728&r1=336727&r2=336728&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=336728&r1=336727&r2=336728&view=diff>>
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 10
> 14:00:22 2018
> @@ -305,15 +305,6 @@ let Predicates = [UseAVX] in {
> def : Pat<(v2f64 (X86Movsd VR128:$src1,
> (scalar_to_vector FR64:$src2))),
> (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS
> FR64:$src2, VR128))>;
> -
> - // FIXME: Instead of a X86Movlps there should be a
> X86Movsd here, the problem
> - // is during lowering, where it's not possible to
> recognize the fold cause
> - // it has two uses through a bitcast. One use
> disappears
> at isel time and the
> - // fold opportunity reappears.
> - def : Pat<(v2f64 (X86Movlpd VR128:$src1,
> VR128:$src2)),
> - (VMOVSDrr VR128:$src1, VR128:$src2)>;
> - def : Pat<(v4f32 (X86Movlps VR128:$src1,
> VR128:$src2)),
> - (VMOVSDrr VR128:$src1, VR128:$src2)>;
> }
> let Predicates = [UseSSE1] in {
> @@ -372,15 +363,6 @@ let Predicates = [UseSSE2] in {
> def : Pat<(v2f64 (X86Movsd VR128:$src1,
> (scalar_to_vector FR64:$src2))),
> (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS
> FR64:$src2, VR128))>;
> -
> - // FIXME: Instead of a X86Movlps there should be a
> X86Movsd here, the problem
> - // is during lowering, where it's not possible to
> recognize the fold because
> - // it has two uses through a bitcast. One use
> disappears
> at isel time and the
> - // fold opportunity reappears.
> - def : Pat<(v2f64 (X86Movlpd VR128:$src1,
> VR128:$src2)),
> - (MOVSDrr VR128:$src1, VR128:$src2)>;
> - def : Pat<(v4f32 (X86Movlps VR128:$src1,
> VR128:$src2)),
> - (MOVSDrr VR128:$src1, VR128:$src2)>;
> }
> // Aliases to help the assembler pick two byte VEX
> encodings by swapping the
> @@ -692,8 +674,8 @@ multiclass
> sse12_mov_hilo_packed_base<bi
> Sched<[SchedWriteFShuffle.XMM.Folded,
> ReadAfterLd]>;
> }
> -multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode
> psnode, SDNode pdnode,
> - string base_opc> {
> +multiclass sse12_mov_hilo_packed<bits<8>opc,
> SDPatternOperator psnode,
> + SDPatternOperator
> pdnode,
> string base_opc> {
> let Predicates = [UseAVX] in
> defm V#NAME :
> sse12_mov_hilo_packed_base<opc, psnode,
> pdnode, base_opc,
> "\t{$src2,
> $src1,
> $dst|$dst, $src1, $src2}">,
> @@ -704,7 +686,7 @@ multiclass
> sse12_mov_hilo_packed<bits<8>
> "\t{$src2,
> $dst|$dst,
> $src2}">;
> }
> -defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps,
> X86Movlpd, "movlp">;
> +defm MOVL : sse12_mov_hilo_packed<0x12, null_frag,
> null_frag, "movlp">;
> let SchedRW = [WriteFStore] in {
> let Predicates = [UseAVX] in {
> @@ -730,24 +712,10 @@ def MOVLPDmr : PDI<0x13,
> MRMDestMem, (ou
> } // SchedRW
> let Predicates = [UseAVX] in {
> - // Shuffle with VMOVLPS
> - def : Pat<(v4f32 (X86Movlps VR128:$src1, (load
> addr:$src2))),
> - (VMOVLPSrm VR128:$src1, addr:$src2)>;
> -
> // Shuffle with VMOVLPD
> - def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load
> addr:$src2))),
> - (VMOVLPDrm VR128:$src1, addr:$src2)>;
> def : Pat<(v2f64 (X86Movsd VR128:$src1,
> (v2f64
> (scalar_to_vector
> (loadf64 addr:$src2))))),
> (VMOVLPDrm VR128:$src1, addr:$src2)>;
> -
> - // Store patterns
> - def : Pat<(store (v4f32 (X86Movlps (load
> addr:$src1),
> VR128:$src2)),
> - addr:$src1),
> - (VMOVLPSmr addr:$src1, VR128:$src2)>;
> - def : Pat<(store (v2f64 (X86Movlpd (load
> addr:$src1),
> VR128:$src2)),
> - addr:$src1),
> - (VMOVLPDmr addr:$src1, VR128:$src2)>;
> }
> let Predicates = [UseSSE1] in {
> @@ -755,32 +723,13 @@ let Predicates = [UseSSE1] in {
> def : Pat<(store (i64 (extractelt (bc_v2i64 (v4f32
> VR128:$src2)),
> (iPTR 0))),
> addr:$src1),
> (MOVLPSmr addr:$src1, VR128:$src2)>;
> -
> - // Shuffle with MOVLPS
> - def : Pat<(v4f32 (X86Movlps VR128:$src1, (load
> addr:$src2))),
> - (MOVLPSrm VR128:$src1, addr:$src2)>;
> - def : Pat<(X86Movlps VR128:$src1,
> - (bc_v4f32 (v2i64
> (scalar_to_vector
> (loadi64 addr:$src2))))),
> - (MOVLPSrm VR128:$src1, addr:$src2)>;
> -
> - // Store patterns
> - def : Pat<(store (v4f32 (X86Movlps (load
> addr:$src1),
> VR128:$src2)),
> - addr:$src1),
> - (MOVLPSmr addr:$src1, VR128:$src2)>;
> }
> let Predicates = [UseSSE2] in {
> // Shuffle with MOVLPD
> - def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load
> addr:$src2))),
> - (MOVLPDrm VR128:$src1, addr:$src2)>;
> def : Pat<(v2f64 (X86Movsd VR128:$src1,
> (v2f64
> (scalar_to_vector
> (loadf64 addr:$src2))))),
> (MOVLPDrm VR128:$src1, addr:$src2)>;
> -
> - // Store patterns
> - def : Pat<(store (v2f64 (X86Movlpd (load
> addr:$src1),
> VR128:$src2)),
> - addr:$src1),
> - (MOVLPDmr addr:$src1, VR128:$src2)>;
> }
>
> //===----------------------------------------------------------------------===//
>
>
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