[PATCH] D49065: AMDGPU: Stop wasting argument registers with v3i32/v3f32

[Marek Olšák via Phabricator via llvm-commits]

mareko added inline comments.


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Comment at: test/CodeGen/AMDGPU/ret.ll:165
+; GCN: v_mov_b32_e32 v3, v5
 ; GCN-NOT: s_endpgm
 define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr418([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #4 {
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This can't be changed. <3 x i32> is a valid function argument type meaning 3 input VGPRs.  There is no wasted space. It declares exactly 3 VGPRs. The VGPR indices are hardcoded in the hardware and can't be adjusted.


https://reviews.llvm.org/D49065