[PATCH] D49026: [AMDGPU] New tbuffer intrinsics

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added subscribers: llvm-commits, t-tye, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

This commit adds new intrinsics

  llvm.amdgcn.tbuffer2.load
  llvm.amdgcn.tbuffer2.store

with combined operands for format (dfmt+nfmt) and cachepolicy (glc+slc).

The AMDISD::TBUFFER_* SD nodes have changed correspondingly.

The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store
intrinsics continue to work.

Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4


Repository:
  rL LLVM

https://reviews.llvm.org/D49026

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/BUFInstructions.td
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer2.load.d16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer2.load.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer2.store.d16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer2.store.ll

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