[PATCH] D48970: [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, YuanLin, lebedev.ri, robertlytton.
Herald added subscribers: nhaehnle, nemanjai, mcrosier.
Herald added a reviewer: javed.absar.

This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too.

The motivation comes from reduced bit-hacking for select-of-constants in IR after https://reviews.llvm.org/rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html

The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests.

Note the asymmetry: I didn't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction.

I don't know if the XCore test diff is a regression, but given that we canonicalize IR to this form, I'd think that could be changed independently if needed.


https://reviews.llvm.org/D48970

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/signbit-shift.ll
  test/CodeGen/AMDGPU/commute-compares.ll
  test/CodeGen/PowerPC/signbit-shift.ll
  test/CodeGen/PowerPC/testComparesigesll.ll
  test/CodeGen/PowerPC/testComparesllgesll.ll
  test/CodeGen/X86/select.ll
  test/CodeGen/X86/selectcc-to-shiftand.ll
  test/CodeGen/X86/signbit-shift.ll
  test/CodeGen/XCore/ashr.ll

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