[llvm] r336265 - [AArch64][SVE] Asm: Support for FP conversion instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 4 05:13:18 PDT 2018
Author: s.desmalen
Date: Wed Jul 4 05:13:17 2018
New Revision: 336265
URL: http://llvm.org/viewvc/llvm-project?rev=336265&view=rev
Log:
[AArch64][SVE] Asm: Support for FP conversion instructions.
The variants added are:
- fcvt (FP convert precision)
- scvtf (signed int -> FP)
- ucvtf (unsigned int -> FP)
- fcvtzs (FP -> signed int (round to zero))
- fcvtzu (FP -> unsigned int (round to zero))
For example:
fcvt z0.h, p0/m, z0.s (single- to half-precision FP)
scvtf z0.h, p0/m, z0.s (32-bit int to half-precision FP)
ucvtf z0.h, p0/m, z0.s (32-bit unsigned int to half-precision FP)
fcvtzs z0.s, p0/m, z0.h (half-precision FP to 32-bit int)
fcvtzu z0.s, p0/m, z0.h (half-precision FP to 32-bit unsigned int)
Added:
llvm/trunk/test/MC/AArch64/SVE/fcvt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcvt.s
llvm/trunk/test/MC/AArch64/SVE/fcvtzs-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcvtzs.s
llvm/trunk/test/MC/AArch64/SVE/fcvtzu-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcvtzu.s
llvm/trunk/test/MC/AArch64/SVE/scvtf-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/scvtf.s
llvm/trunk/test/MC/AArch64/SVE/ucvtf-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ucvtf.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=336265&r1=336264&r2=336265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Wed Jul 4 05:13:17 2018
@@ -660,6 +660,41 @@ let Predicates = [HasSVE] in {
defm LSR_ZPmZ : sve_int_bin_pred_shift_1<0b001, "lsr">;
defm LSL_ZPmZ : sve_int_bin_pred_shift_1<0b011, "lsl">;
+ def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16>;
+ def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32>;
+ def SCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110010, "scvtf", ZPR16, ZPR16>;
+ def SCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010100, "scvtf", ZPR32, ZPR32>;
+ def UCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010101, "ucvtf", ZPR32, ZPR32>;
+ def UCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110011, "ucvtf", ZPR16, ZPR16>;
+ def FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16>;
+ def FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32>;
+ def FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16>;
+ def FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32>;
+ def FCVT_ZPmZ_DtoH : sve_fp_2op_p_zd<0b1101000, "fcvt", ZPR64, ZPR16>;
+ def FCVT_ZPmZ_HtoD : sve_fp_2op_p_zd<0b1101001, "fcvt", ZPR16, ZPR64>;
+ def FCVT_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1101010, "fcvt", ZPR64, ZPR32>;
+ def FCVT_ZPmZ_StoD : sve_fp_2op_p_zd<0b1101011, "fcvt", ZPR32, ZPR64>;
+ def SCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110000, "scvtf", ZPR32, ZPR64>;
+ def UCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110001, "ucvtf", ZPR32, ZPR64>;
+ def UCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110101, "ucvtf", ZPR32, ZPR16>;
+ def SCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110100, "scvtf", ZPR64, ZPR32>;
+ def SCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110100, "scvtf", ZPR32, ZPR16>;
+ def SCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110110, "scvtf", ZPR64, ZPR16>;
+ def UCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110101, "ucvtf", ZPR64, ZPR32>;
+ def UCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110111, "ucvtf", ZPR64, ZPR16>;
+ def SCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110110, "scvtf", ZPR64, ZPR64>;
+ def UCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110111, "ucvtf", ZPR64, ZPR64>;
+ def FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32>;
+ def FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32>;
+ def FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64>;
+ def FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32>;
+ def FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64>;
+ def FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32>;
+ def FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64>;
+ def FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64>;
+ def FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64>;
+ def FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64>;
+
// InstAliases
def : InstAlias<"mov $Zd, $Zn",
(ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=336265&r1=336264&r2=336265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Wed Jul 4 05:13:17 2018
@@ -994,6 +994,32 @@ multiclass sve_int_perm_bin_perm_zz<bits
}
//===----------------------------------------------------------------------===//
+// SVE Floating Point Unary Operations Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
+ RegisterOperand o_zprtype>
+: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
+ asm, "\t$Zd, $Pg/m, $Zn",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Zd;
+ bits<5> Zn;
+ let Inst{31-24} = 0b01100101;
+ let Inst{23-22} = opc{6-5};
+ let Inst{21} = 0b0;
+ let Inst{20-16} = opc{4-0};
+ let Inst{15-13} = 0b101;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+
+ let Constraints = "$Zd = $_Zd";
+}
+
+
+//===----------------------------------------------------------------------===//
// SVE Integer Arithmetic - Binary Predicated Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE/fcvt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcvt-diagnostics.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcvt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcvt-diagnostics.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,25 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcvt z0.h, p0/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvt z0.h, p0/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcvt z0.s, p0/m, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvt z0.s, p0/m, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcvt z0.d, p0/m, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvt z0.d, p0/m, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+fcvt z0.h, p8/m, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fcvt z0.h, p8/m, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcvt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcvt.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcvt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcvt.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcvt z0.h, p0/m, z0.s
+// CHECK-INST: fcvt z0.h, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x88,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 88 65 <unknown>
+
+fcvt z0.h, p0/m, z0.d
+// CHECK-INST: fcvt z0.h, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xc8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c8 65 <unknown>
+
+fcvt z0.s, p0/m, z0.h
+// CHECK-INST: fcvt z0.s, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x89,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 89 65 <unknown>
+
+fcvt z0.s, p0/m, z0.d
+// CHECK-INST: fcvt z0.s, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xca,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 ca 65 <unknown>
+
+fcvt z0.d, p0/m, z0.h
+// CHECK-INST: fcvt z0.d, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0xc9,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c9 65 <unknown>
+
+fcvt z0.d, p0/m, z0.s
+// CHECK-INST: fcvt z0.d, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xcb,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 cb 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcvtzs-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcvtzs-diagnostics.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcvtzs-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcvtzs-diagnostics.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcvtzs z0.h, p0/m, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzs z0.h, p0/m, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcvtzs z0.h, p0/m, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzs z0.h, p0/m, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+fcvtzs z0.h, p8/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fcvtzs z0.h, p8/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcvtzs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcvtzs.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcvtzs.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcvtzs.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcvtzs z0.h, p0/m, z0.h
+// CHECK-INST: fcvtzs z0.h, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x5a,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 5a 65 <unknown>
+
+fcvtzs z0.s, p0/m, z0.h
+// CHECK-INST: fcvtzs z0.s, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x5c,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 5c 65 <unknown>
+
+fcvtzs z0.s, p0/m, z0.s
+// CHECK-INST: fcvtzs z0.s, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x9c,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 9c 65 <unknown>
+
+fcvtzs z0.s, p0/m, z0.d
+// CHECK-INST: fcvtzs z0.s, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d8 65 <unknown>
+
+fcvtzs z0.d, p0/m, z0.h
+// CHECK-INST: fcvtzs z0.d, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x5e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 5e 65 <unknown>
+
+fcvtzs z0.d, p0/m, z0.s
+// CHECK-INST: fcvtzs z0.d, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xdc,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 dc 65 <unknown>
+
+fcvtzs z0.d, p0/m, z0.d
+// CHECK-INST: fcvtzs z0.d, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xde,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 de 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcvtzu-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcvtzu-diagnostics.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcvtzu-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcvtzu-diagnostics.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcvtzu z0.h, p0/m, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzu z0.h, p0/m, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcvtzu z0.h, p0/m, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzu z0.h, p0/m, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+fcvtzu z0.h, p8/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fcvtzu z0.h, p8/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcvtzu.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcvtzu.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcvtzu.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcvtzu.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcvtzu z0.h, p0/m, z0.h
+// CHECK-INST: fcvtzu z0.h, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x5b,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 5b 65 <unknown>
+
+fcvtzu z0.s, p0/m, z0.h
+// CHECK-INST: fcvtzu z0.s, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x5d,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 5d 65 <unknown>
+
+fcvtzu z0.s, p0/m, z0.s
+// CHECK-INST: fcvtzu z0.s, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x9d,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 9d 65 <unknown>
+
+fcvtzu z0.s, p0/m, z0.d
+// CHECK-INST: fcvtzu z0.s, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd9,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d9 65 <unknown>
+
+fcvtzu z0.d, p0/m, z0.h
+// CHECK-INST: fcvtzu z0.d, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 5f 65 <unknown>
+
+fcvtzu z0.d, p0/m, z0.s
+// CHECK-INST: fcvtzu z0.d, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xdd,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 dd 65 <unknown>
+
+fcvtzu z0.d, p0/m, z0.d
+// CHECK-INST: fcvtzu z0.d, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 df 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/scvtf-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/scvtf-diagnostics.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/scvtf-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/scvtf-diagnostics.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+scvtf z0.s, p0/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: scvtf z0.s, p0/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+scvtf z0.d, p0/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: scvtf z0.d, p0/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+scvtf z0.h, p8/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: scvtf z0.h, p8/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/scvtf.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/scvtf.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/scvtf.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/scvtf.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+scvtf z0.h, p0/m, z0.h
+// CHECK-INST: scvtf z0.h, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x52,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 52 65 <unknown>
+
+scvtf z0.h, p0/m, z0.s
+// CHECK-INST: scvtf z0.h, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x54,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 54 65 <unknown>
+
+scvtf z0.h, p0/m, z0.d
+// CHECK-INST: scvtf z0.h, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0x56,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 56 65 <unknown>
+
+scvtf z0.s, p0/m, z0.s
+// CHECK-INST: scvtf z0.s, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x94,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 94 65 <unknown>
+
+scvtf z0.s, p0/m, z0.d
+// CHECK-INST: scvtf z0.s, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd4,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d4 65 <unknown>
+
+scvtf z0.d, p0/m, z0.s
+// CHECK-INST: scvtf z0.d, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xd0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d0 65 <unknown>
+
+scvtf z0.d, p0/m, z0.d
+// CHECK-INST: scvtf z0.d, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd6,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d6 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ucvtf-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ucvtf-diagnostics.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ucvtf-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ucvtf-diagnostics.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+ucvtf z0.s, p0/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ucvtf z0.s, p0/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ucvtf z0.d, p0/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ucvtf z0.d, p0/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+ucvtf z0.h, p8/m, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ucvtf z0.h, p8/m, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ucvtf.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ucvtf.s?rev=336265&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ucvtf.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ucvtf.s Wed Jul 4 05:13:17 2018
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ucvtf z0.h, p0/m, z0.h
+// CHECK-INST: ucvtf z0.h, p0/m, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x53,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 53 65 <unknown>
+
+ucvtf z0.h, p0/m, z0.s
+// CHECK-INST: ucvtf z0.h, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x55,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 55 65 <unknown>
+
+ucvtf z0.h, p0/m, z0.d
+// CHECK-INST: ucvtf z0.h, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0x57,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 57 65 <unknown>
+
+ucvtf z0.s, p0/m, z0.s
+// CHECK-INST: ucvtf z0.s, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x95,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 95 65 <unknown>
+
+ucvtf z0.s, p0/m, z0.d
+// CHECK-INST: ucvtf z0.s, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd5,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d5 65 <unknown>
+
+ucvtf z0.d, p0/m, z0.s
+// CHECK-INST: ucvtf z0.d, p0/m, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xd1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d1 65 <unknown>
+
+ucvtf z0.d, p0/m, z0.d
+// CHECK-INST: ucvtf z0.d, p0/m, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd7,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d7 65 <unknown>
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