[llvm] r336193 - [AArch64] Armv8.4-A: system registers
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 3 05:09:20 PDT 2018
Author: sjoerdmeijer
Date: Tue Jul 3 05:09:20 2018
New Revision: 336193
URL: http://llvm.org/viewvc/llvm-project?rev=336193&view=rev
Log:
[AArch64] Armv8.4-A: system registers
This adds the following system registers:
- RAS registers,
- MPAM registers,
- Activitiy monitor registers,
- Trace Extension registers,
- Timing insensitivity of data processing instructions,
- Enhanced Support for Nested Virtualization.
Differential Revision: https://reviews.llvm.org/D48871
Added:
llvm/trunk/test/MC/AArch64/armv8.4a-actmon.s
llvm/trunk/test/MC/AArch64/armv8.4a-dit.s
llvm/trunk/test/MC/AArch64/armv8.4a-mpam.s
llvm/trunk/test/MC/AArch64/armv8.4a-ras.s
llvm/trunk/test/MC/AArch64/armv8.4a-trace.s
llvm/trunk/test/MC/AArch64/armv8.4a-vncr.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt
llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=336193&r1=336192&r2=336193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Tue Jul 3 05:09:20 2018
@@ -278,7 +278,9 @@ def : PState<"PAN", 0b00100>;
// v8.2a "User Access Override" extension-specific PStates
let Requires = [{ {AArch64::HasV8_2aOps} }] in
def : PState<"UAO", 0b00011>;
-
+// v8.4a timining insensitivity of data processing instructions
+let Requires = [{ {AArch64::HasV8_4aOps} }] in
+def : PState<"DIT", 0b11010>;
//===----------------------------------------------------------------------===//
// PSB instruction options.
@@ -1138,6 +1140,104 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11,
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
+// v8.4a RAS registers
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
+def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
+def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>;
+def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;
+def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;
+def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
+
+// v8.4a MPAM registers
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
+def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;
+def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>;
+def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>;
+def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>;
+def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>;
+def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>;
+def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>;
+def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>;
+def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;
+def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;
+def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
+
+// v8.4a Activitiy monitor registers
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>;
+def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>;
+def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>;
+def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>;
+def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>;
+def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>;
+def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>;
+def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>;
+def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>;
+def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>;
+def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>;
+def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>;
+def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>;
+def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>;
+def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>;
+def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>;
+def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>;
+def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>;
+def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>;
+def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>;
+def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>;
+def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>;
+def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>;
+def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>;
+def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>;
+def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>;
+def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>;
+def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>;
+def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>;
+def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>;
+def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>;
+def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>;
+def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>;
+def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>;
+def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>;
+def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>;
+def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>;
+def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>;
+def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>;
+def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>;
+def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>;
+def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>;
+def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>;
+def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>;
+def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>;
+def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>;
+def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>;
+def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;
+
+// v8.4a Trace Extension registers
+//
+// Please note that the 8.4 spec also defines these registers:
+// TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3,
+// but they are already defined above.
+//
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>;
+def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>;
+def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>;
+
+// v8.4a Timining insensitivity of data processing instructions
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>;
+
+// v8.4a Enhanced Support for Nested Virtualization
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>;
+
} // HasV8_4aOps
// Cyclone specific system registers
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=336193&r1=336192&r2=336193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Tue Jul 3 05:09:20 2018
@@ -922,6 +922,7 @@ public:
bool isSystemPStateFieldWithImm0_1() const {
if (!isSysReg()) return false;
return (SysReg.PStateField == AArch64PState::PAN ||
+ SysReg.PStateField == AArch64PState::DIT ||
SysReg.PStateField == AArch64PState::UAO);
}
Added: llvm/trunk/test/MC/AArch64/armv8.4a-actmon.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-actmon.s?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.4a-actmon.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.4a-actmon.s Tue Jul 3 05:09:20 2018
@@ -0,0 +1,509 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A Activity Monitors
+//------------------------------------------------------------------------------
+
+msr AMCR_EL0, x0
+msr AMCFGR_EL0, x0
+msr AMCGCR_EL0, x0
+msr AMUSERENR_EL0, x0
+msr AMCNTENCLR0_EL0, x0
+msr AMCNTENSET0_EL0, x0
+msr AMEVCNTR00_EL0, x0
+msr AMEVCNTR01_EL0, x0
+msr AMEVCNTR02_EL0, x0
+msr AMEVCNTR03_EL0, x0
+msr AMEVTYPER00_EL0, x0
+msr AMEVTYPER01_EL0, x0
+msr AMEVTYPER02_EL0, x0
+msr AMEVTYPER03_EL0, x0
+msr AMCNTENCLR1_EL0, x0
+msr AMCNTENSET1_EL0, x0
+msr AMEVCNTR10_EL0, x0
+msr AMEVCNTR11_EL0, x0
+msr AMEVCNTR12_EL0, x0
+msr AMEVCNTR13_EL0, x0
+msr AMEVCNTR14_EL0, x0
+msr AMEVCNTR15_EL0, x0
+msr AMEVCNTR16_EL0, x0
+msr AMEVCNTR17_EL0, x0
+msr AMEVCNTR18_EL0, x0
+msr AMEVCNTR19_EL0, x0
+msr AMEVCNTR110_EL0, x0
+msr AMEVCNTR111_EL0, x0
+msr AMEVCNTR112_EL0, x0
+msr AMEVCNTR113_EL0, x0
+msr AMEVCNTR114_EL0, x0
+msr AMEVCNTR115_EL0, x0
+msr AMEVTYPER10_EL0, x0
+msr AMEVTYPER11_EL0, x0
+msr AMEVTYPER12_EL0, x0
+msr AMEVTYPER13_EL0, x0
+msr AMEVTYPER14_EL0, x0
+msr AMEVTYPER15_EL0, x0
+msr AMEVTYPER16_EL0, x0
+msr AMEVTYPER17_EL0, x0
+msr AMEVTYPER18_EL0, x0
+msr AMEVTYPER19_EL0, x0
+msr AMEVTYPER110_EL0, x0
+msr AMEVTYPER111_EL0, x0
+msr AMEVTYPER112_EL0, x0
+msr AMEVTYPER113_EL0, x0
+msr AMEVTYPER114_EL0, x0
+msr AMEVTYPER115_EL0, x0
+
+mrs x0, AMCR_EL0
+mrs x0, AMCFGR_EL0
+mrs x0, AMCGCR_EL0
+mrs x0, AMUSERENR_EL0
+mrs x0, AMCNTENCLR0_EL0
+mrs x0, AMCNTENSET0_EL0
+mrs x0, AMEVCNTR00_EL0
+mrs x0, AMEVCNTR01_EL0
+mrs x0, AMEVCNTR02_EL0
+mrs x0, AMEVCNTR03_EL0
+mrs x0, AMEVTYPER00_EL0
+mrs x0, AMEVTYPER01_EL0
+mrs x0, AMEVTYPER02_EL0
+mrs x0, AMEVTYPER03_EL0
+mrs x0, AMCNTENCLR1_EL0
+mrs x0, AMCNTENSET1_EL0
+mrs x0, AMEVCNTR10_EL0
+mrs x0, AMEVCNTR11_EL0
+mrs x0, AMEVCNTR12_EL0
+mrs x0, AMEVCNTR13_EL0
+mrs x0, AMEVCNTR14_EL0
+mrs x0, AMEVCNTR15_EL0
+mrs x0, AMEVCNTR16_EL0
+mrs x0, AMEVCNTR17_EL0
+mrs x0, AMEVCNTR18_EL0
+mrs x0, AMEVCNTR19_EL0
+mrs x0, AMEVCNTR110_EL0
+mrs x0, AMEVCNTR111_EL0
+mrs x0, AMEVCNTR112_EL0
+mrs x0, AMEVCNTR113_EL0
+mrs x0, AMEVCNTR114_EL0
+mrs x0, AMEVCNTR115_EL0
+mrs x0, AMEVTYPER10_EL0
+mrs x0, AMEVTYPER11_EL0
+mrs x0, AMEVTYPER12_EL0
+mrs x0, AMEVTYPER13_EL0
+mrs x0, AMEVTYPER14_EL0
+mrs x0, AMEVTYPER15_EL0
+mrs x0, AMEVTYPER16_EL0
+mrs x0, AMEVTYPER17_EL0
+mrs x0, AMEVTYPER18_EL0
+mrs x0, AMEVTYPER19_EL0
+mrs x0, AMEVTYPER110_EL0
+mrs x0, AMEVTYPER111_EL0
+mrs x0, AMEVTYPER112_EL0
+mrs x0, AMEVTYPER113_EL0
+mrs x0, AMEVTYPER114_EL0
+mrs x0, AMEVTYPER115_EL0
+
+
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr AMCFGR_EL0, x0
+//CHECK-RO: ^
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr AMCGCR_EL0, x0
+//CHECK-RO: ^
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr AMEVTYPER00_EL0, x0
+//CHECK-RO: ^
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr AMEVTYPER01_EL0, x0
+//CHECK-RO: ^
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr AMEVTYPER02_EL0, x0
+//CHECK-RO: ^
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr AMEVTYPER03_EL0, x0
+//CHECK-RO: ^
+
+
+//CHECK: msr AMCR_EL0, x0 // encoding: [0x00,0xd2,0x1b,0xd5]
+//CHECK: msr AMUSERENR_EL0, x0 // encoding: [0x60,0xd2,0x1b,0xd5]
+//CHECK: msr AMCNTENCLR0_EL0, x0 // encoding: [0x80,0xd2,0x1b,0xd5]
+//CHECK: msr AMCNTENSET0_EL0, x0 // encoding: [0xa0,0xd2,0x1b,0xd5]
+//CHECK: msr AMEVCNTR00_EL0, x0 // encoding: [0x00,0xd4,0x1b,0xd5]
+//CHECK: msr AMEVCNTR01_EL0, x0 // encoding: [0x20,0xd4,0x1b,0xd5]
+//CHECK: msr AMEVCNTR02_EL0, x0 // encoding: [0x40,0xd4,0x1b,0xd5]
+//CHECK: msr AMEVCNTR03_EL0, x0 // encoding: [0x60,0xd4,0x1b,0xd5]
+//CHECK: msr AMCNTENCLR1_EL0, x0 // encoding: [0x00,0xd3,0x1b,0xd5]
+//CHECK: msr AMCNTENSET1_EL0, x0 // encoding: [0x20,0xd3,0x1b,0xd5]
+//CHECK: msr AMEVCNTR10_EL0, x0 // encoding: [0x00,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR11_EL0, x0 // encoding: [0x20,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR12_EL0, x0 // encoding: [0x40,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR13_EL0, x0 // encoding: [0x60,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR14_EL0, x0 // encoding: [0x80,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR15_EL0, x0 // encoding: [0xa0,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR16_EL0, x0 // encoding: [0xc0,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR17_EL0, x0 // encoding: [0xe0,0xdc,0x1b,0xd5]
+//CHECK: msr AMEVCNTR18_EL0, x0 // encoding: [0x00,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR19_EL0, x0 // encoding: [0x20,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR110_EL0, x0 // encoding: [0x40,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR111_EL0, x0 // encoding: [0x60,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR112_EL0, x0 // encoding: [0x80,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR113_EL0, x0 // encoding: [0xa0,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR114_EL0, x0 // encoding: [0xc0,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVCNTR115_EL0, x0 // encoding: [0xe0,0xdd,0x1b,0xd5]
+//CHECK: msr AMEVTYPER10_EL0, x0 // encoding: [0x00,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER11_EL0, x0 // encoding: [0x20,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER12_EL0, x0 // encoding: [0x40,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER13_EL0, x0 // encoding: [0x60,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER14_EL0, x0 // encoding: [0x80,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER15_EL0, x0 // encoding: [0xa0,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER16_EL0, x0 // encoding: [0xc0,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER17_EL0, x0 // encoding: [0xe0,0xde,0x1b,0xd5]
+//CHECK: msr AMEVTYPER18_EL0, x0 // encoding: [0x00,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER19_EL0, x0 // encoding: [0x20,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER110_EL0, x0 // encoding: [0x40,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER111_EL0, x0 // encoding: [0x60,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER112_EL0, x0 // encoding: [0x80,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER113_EL0, x0 // encoding: [0xa0,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER114_EL0, x0 // encoding: [0xc0,0xdf,0x1b,0xd5]
+//CHECK: msr AMEVTYPER115_EL0, x0 // encoding: [0xe0,0xdf,0x1b,0xd5]
+
+//CHECK: mrs x0, AMCR_EL0 // encoding: [0x00,0xd2,0x3b,0xd5]
+//CHECK: mrs x0, AMCFGR_EL0 // encoding: [0x20,0xd2,0x3b,0xd5]
+//CHECK: mrs x0, AMCGCR_EL0 // encoding: [0x40,0xd2,0x3b,0xd5]
+//CHECK: mrs x0, AMUSERENR_EL0 // encoding: [0x60,0xd2,0x3b,0xd5]
+//CHECK: mrs x0, AMCNTENCLR0_EL0 // encoding: [0x80,0xd2,0x3b,0xd5]
+//CHECK: mrs x0, AMCNTENSET0_EL0 // encoding: [0xa0,0xd2,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR00_EL0 // encoding: [0x00,0xd4,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR01_EL0 // encoding: [0x20,0xd4,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR02_EL0 // encoding: [0x40,0xd4,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR03_EL0 // encoding: [0x60,0xd4,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER00_EL0 // encoding: [0x00,0xd6,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER01_EL0 // encoding: [0x20,0xd6,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER02_EL0 // encoding: [0x40,0xd6,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER03_EL0 // encoding: [0x60,0xd6,0x3b,0xd5]
+//CHECK: mrs x0, AMCNTENCLR1_EL0 // encoding: [0x00,0xd3,0x3b,0xd5]
+//CHECK: mrs x0, AMCNTENSET1_EL0 // encoding: [0x20,0xd3,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR10_EL0 // encoding: [0x00,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR11_EL0 // encoding: [0x20,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR12_EL0 // encoding: [0x40,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR13_EL0 // encoding: [0x60,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR14_EL0 // encoding: [0x80,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR15_EL0 // encoding: [0xa0,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR16_EL0 // encoding: [0xc0,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR17_EL0 // encoding: [0xe0,0xdc,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR18_EL0 // encoding: [0x00,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR19_EL0 // encoding: [0x20,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR110_EL0 // encoding: [0x40,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR111_EL0 // encoding: [0x60,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR112_EL0 // encoding: [0x80,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR113_EL0 // encoding: [0xa0,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR114_EL0 // encoding: [0xc0,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVCNTR115_EL0 // encoding: [0xe0,0xdd,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER10_EL0 // encoding: [0x00,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER11_EL0 // encoding: [0x20,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER12_EL0 // encoding: [0x40,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER13_EL0 // encoding: [0x60,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER14_EL0 // encoding: [0x80,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER15_EL0 // encoding: [0xa0,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER16_EL0 // encoding: [0xc0,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER17_EL0 // encoding: [0xe0,0xde,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER18_EL0 // encoding: [0x00,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER19_EL0 // encoding: [0x20,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER110_EL0 // encoding: [0x40,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER111_EL0 // encoding: [0x60,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER112_EL0 // encoding: [0x80,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER113_EL0 // encoding: [0xa0,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER114_EL0 // encoding: [0xc0,0xdf,0x3b,0xd5]
+//CHECK: mrs x0, AMEVTYPER115_EL0 // encoding: [0xe0,0xdf,0x3b,0xd5]
+
+
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCR_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCFGR_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCGCR_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMUSERENR_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCNTENCLR0_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCNTENSET0_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR00_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR01_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR02_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR03_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER00_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER01_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER02_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER03_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCNTENCLR1_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMCNTENSET1_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR10_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR11_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR12_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR13_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR14_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR15_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR16_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR17_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR18_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR19_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR110_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR111_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR112_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR113_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR114_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVCNTR115_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER10_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER11_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER12_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER13_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER14_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER15_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER16_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER17_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER18_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER19_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER110_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER111_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER112_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER113_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER114_EL0, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr AMEVTYPER115_EL0, x0
+//CHECK-ERROR: ^
+
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCR_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCFGR_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCGCR_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMUSERENR_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCNTENCLR0_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCNTENSET0_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR00_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR01_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR02_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR03_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER00_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER01_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER02_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER03_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCNTENCLR1_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMCNTENSET1_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR10_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR11_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR12_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR13_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR14_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR15_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR16_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR17_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR18_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR19_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR110_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR111_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR112_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR113_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR114_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVCNTR115_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER10_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER11_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER12_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER13_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER14_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER15_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER16_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER17_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER18_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER19_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER110_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER111_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER112_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER113_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER114_EL0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, AMEVTYPER115_EL0
+//CHECK-ERROR: ^
Added: llvm/trunk/test/MC/AArch64/armv8.4a-dit.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-dit.s?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.4a-dit.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.4a-dit.s Tue Jul 3 05:09:20 2018
@@ -0,0 +1,42 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A Timing insensitivity of data processing instructions
+//------------------------------------------------------------------------------
+
+msr DIT, #1
+msr DIT, x0
+mrs x0, DIT
+
+//CHECK: msr DIT, #1 // encoding: [0x5f,0x41,0x03,0xd5]
+//CHECK-NEXT: msr DIT, x0 // encoding: [0xa0,0x42,0x1b,0xd5]
+//CHECK-NEXT: mrs x0, DIT // encoding: [0xa0,0x42,0x3b,0xd5]
+
+msr DIT, #2
+msr DIT, #-1
+
+//CHECK-ERROR: error: immediate must be an integer in range [0, 1].
+//CHECK-ERROR-NEXT: msr DIT, #2
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: error: immediate must be an integer in range [0, 1].
+//CHECK-ERROR-NEXT: msr DIT, #-1
+//CHECK-ERROR-NEXT: ^
+
+//CHECK-NO-V84: error: expected writable system register or pstate
+//CHECK-NO-V84-NEXT: msr DIT, #1
+//CHECK-NO-V84-NEXT: ^
+//CHECK-NO-V84-NEXT: error: expected writable system register or pstate
+//CHECK-NO-V84-NEXT: msr DIT, x0
+//CHECK-NO-V84-NEXT: ^
+//CHECK-NO-V84-NEXT: error: expected readable system register
+//CHECK-NO-V84-NEXT: mrs x0, DIT
+//CHECK-NO-V84-NEXT: ^
+//CHECK-NO-V84-NEXT: error: expected writable system register or pstate
+//CHECK-NO-V84-NEXT: msr DIT, #2
+//CHECK-NO-V84-NEXT: ^
+//CHECK-NO-V84-NEXT: error: expected writable system register or pstate
+//CHECK-NO-V84-NEXT: msr DIT, #-1
+//CHECK-NO-V84-NEXT: ^
+
Added: llvm/trunk/test/MC/AArch64/armv8.4a-mpam.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-mpam.s?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.4a-mpam.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.4a-mpam.s Tue Jul 3 05:09:20 2018
@@ -0,0 +1,176 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A MPAM Extensions
+//------------------------------------------------------------------------------
+
+msr MPAM0_EL1, x0
+msr MPAM1_EL1, x0
+msr MPAM2_EL2, x0
+msr MPAM3_EL3, x0
+msr MPAM1_EL12, x0
+msr MPAMHCR_EL2, x0
+msr MPAMVPMV_EL2, x0
+msr MPAMVPM0_EL2, x0
+msr MPAMVPM1_EL2, x0
+msr MPAMVPM2_EL2, x0
+msr MPAMVPM3_EL2, x0
+msr MPAMVPM4_EL2, x0
+msr MPAMVPM5_EL2, x0
+msr MPAMVPM6_EL2, x0
+msr MPAMVPM7_EL2, x0
+msr MPAMIDR_EL1, x0
+
+mrs x0, MPAM0_EL1
+mrs x0, MPAM1_EL1
+mrs x0, MPAM2_EL2
+mrs x0, MPAM3_EL3
+mrs x0, MPAM1_EL12
+mrs x0, MPAMHCR_EL2
+mrs x0, MPAMVPMV_EL2
+mrs x0, MPAMVPM0_EL2
+mrs x0, MPAMVPM1_EL2
+mrs x0, MPAMVPM2_EL2
+mrs x0, MPAMVPM3_EL2
+mrs x0, MPAMVPM4_EL2
+mrs x0, MPAMVPM5_EL2
+mrs x0, MPAMVPM6_EL2
+mrs x0, MPAMVPM7_EL2
+mrs x0, MPAMIDR_EL1
+
+//CHECK: msr MPAM0_EL1, x0 // encoding: [0x20,0xa5,0x18,0xd5]
+//CHECK: msr MPAM1_EL1, x0 // encoding: [0x00,0xa5,0x18,0xd5]
+//CHECK: msr MPAM2_EL2, x0 // encoding: [0x00,0xa5,0x1c,0xd5]
+//CHECK: msr MPAM3_EL3, x0 // encoding: [0x00,0xa5,0x1e,0xd5]
+//CHECK: msr MPAM1_EL12, x0 // encoding: [0x00,0xa5,0x1d,0xd5]
+//CHECK: msr MPAMHCR_EL2, x0 // encoding: [0x00,0xa4,0x1c,0xd5]
+//CHECK: msr MPAMVPMV_EL2, x0 // encoding: [0x20,0xa4,0x1c,0xd5]
+//CHECK: msr MPAMVPM0_EL2, x0 // encoding: [0x00,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM1_EL2, x0 // encoding: [0x20,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM2_EL2, x0 // encoding: [0x40,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM3_EL2, x0 // encoding: [0x60,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM4_EL2, x0 // encoding: [0x80,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM5_EL2, x0 // encoding: [0xa0,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM6_EL2, x0 // encoding: [0xc0,0xa6,0x1c,0xd5]
+//CHECK: msr MPAMVPM7_EL2, x0 // encoding: [0xe0,0xa6,0x1c,0xd5]
+
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr MPAMIDR_EL1, x0
+//CHECK-RO: ^
+
+//CHECK: mrs x0, MPAM0_EL1 // encoding: [0x20,0xa5,0x38,0xd5]
+//CHECK: mrs x0, MPAM1_EL1 // encoding: [0x00,0xa5,0x38,0xd5]
+//CHECK: mrs x0, MPAM2_EL2 // encoding: [0x00,0xa5,0x3c,0xd5]
+//CHECK: mrs x0, MPAM3_EL3 // encoding: [0x00,0xa5,0x3e,0xd5]
+//CHECK: mrs x0, MPAM1_EL12 // encoding: [0x00,0xa5,0x3d,0xd5]
+//CHECK: mrs x0, MPAMHCR_EL2 // encoding: [0x00,0xa4,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPMV_EL2 // encoding: [0x20,0xa4,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM0_EL2 // encoding: [0x00,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM1_EL2 // encoding: [0x20,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM2_EL2 // encoding: [0x40,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM3_EL2 // encoding: [0x60,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM4_EL2 // encoding: [0x80,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM5_EL2 // encoding: [0xa0,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM6_EL2 // encoding: [0xc0,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMVPM7_EL2 // encoding: [0xe0,0xa6,0x3c,0xd5]
+//CHECK: mrs x0, MPAMIDR_EL1 // encoding: [0x80,0xa4,0x38,0xd5]
+
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAM0_EL1, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAM1_EL1, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAM2_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAM3_EL3, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAM1_EL12, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMHCR_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPMV_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM0_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM1_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM2_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM3_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM4_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM5_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM6_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMVPM7_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr MPAMIDR_EL1, x0
+//CHECK-ERROR: ^
+
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAM0_EL1
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAM1_EL1
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAM2_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAM3_EL3
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAM1_EL12
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMHCR_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPMV_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM0_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM1_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM2_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM3_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM4_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM5_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM6_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMVPM7_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, MPAMIDR_EL1
+//CHECK-ERROR: ^
Added: llvm/trunk/test/MC/AArch64/armv8.4a-ras.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-ras.s?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.4a-ras.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.4a-ras.s Tue Jul 3 05:09:20 2018
@@ -0,0 +1,60 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A RAS Extensions
+//------------------------------------------------------------------------------
+
+// Read/Write registers:
+
+ msr ERXPFGCTL_EL1, x0
+ mrs x0,ERXPFGCTL_EL1
+
+//CHECK: msr ERXPFGCTL_EL1, x0 // encoding: [0xa0,0x54,0x18,0xd5]
+//CHECK: mrs x0, ERXPFGCTL_EL1 // encoding: [0xa0,0x54,0x38,0xd5]
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected readable system register
+
+ msr ERXPFGCDN_EL1, x0
+ mrs x0,ERXPFGCDN_EL1
+
+//CHECK: msr ERXPFGCDN_EL1, x0 // encoding: [0xc0,0x54,0x18,0xd5]
+//CHECK: mrs x0, ERXPFGCDN_EL1 // encoding: [0xc0,0x54,0x38,0xd5]
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected readable system register
+
+ msr ERXTS_EL1, x0
+ mrs x0,ERXTS_EL1
+
+//CHECK: msr ERXTS_EL1, x0 // encoding: [0xe0,0x55,0x18,0xd5]
+//CHECK: mrs x0, ERXTS_EL1 // encoding: [0xe0,0x55,0x38,0xd5]
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected readable system register
+
+ msr ERXMISC2_EL1, x0
+ mrs x0, ERXMISC2_EL1
+
+//CHECK: msr ERXMISC2_EL1, x0 // encoding: [0x40,0x55,0x18,0xd5]
+//CHECK: mrs x0, ERXMISC2_EL1 // encoding: [0x40,0x55,0x38,0xd5]
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected readable system register
+
+ msr ERXMISC3_EL1, x0
+ mrs x0, ERXMISC3_EL1
+
+//CHECK: msr ERXMISC3_EL1, x0 // encoding: [0x60,0x55,0x18,0xd5]
+//CHECK: mrs x0, ERXMISC3_EL1 // encoding: [0x60,0x55,0x38,0xd5]
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected readable system register
+
+// Read-only registers:
+
+ mrs x0,ERXPFGF_EL1
+ msr ERXPFGF_EL1, x0
+
+//CHECK: mrs x0, ERXPFGF_EL1 // encoding: [0x80,0x54,0x38,0xd5]
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: error: expected writable system register or pstate
Added: llvm/trunk/test/MC/AArch64/armv8.4a-trace.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-trace.s?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.4a-trace.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.4a-trace.s Tue Jul 3 05:09:20 2018
@@ -0,0 +1,42 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A Debug, Trace and PMU Extensions
+//------------------------------------------------------------------------------
+
+msr TRFCR_EL1, x0
+msr TRFCR_EL2, x0
+msr TRFCR_EL12, x0
+
+mrs x0, TRFCR_EL1
+mrs x0, TRFCR_EL2
+mrs x0, TRFCR_EL12
+
+//CHECK: msr TRFCR_EL1, x0 // encoding: [0x20,0x12,0x18,0xd5]
+//CHECK: msr TRFCR_EL2, x0 // encoding: [0x20,0x12,0x1c,0xd5]
+//CHECK: msr TRFCR_EL12, x0 // encoding: [0x20,0x12,0x1d,0xd5]
+
+//CHECK: mrs x0, TRFCR_EL1 // encoding: [0x20,0x12,0x38,0xd5]
+//CHECK: mrs x0, TRFCR_EL2 // encoding: [0x20,0x12,0x3c,0xd5]
+//CHECK: mrs x0, TRFCR_EL12 // encoding: [0x20,0x12,0x3d,0xd5]
+
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr TRFCR_EL1, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr TRFCR_EL2, x0
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: msr TRFCR_EL12, x0
+//CHECK-ERROR: ^
+
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, TRFCR_EL1
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, TRFCR_EL2
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: expected readable system register
+//CHECK-ERROR: mrs x0, TRFCR_EL12
+//CHECK-ERROR: ^
Added: llvm/trunk/test/MC/AArch64/armv8.4a-vncr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.4a-vncr.s?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.4a-vncr.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.4a-vncr.s Tue Jul 3 05:09:20 2018
@@ -0,0 +1,19 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A Enhanced Support for Nested Virtualization
+//------------------------------------------------------------------------------
+
+mrs x0, VNCR_EL2
+msr VNCR_EL2, x0
+
+// CHECK: mrs x0, VNCR_EL2 // encoding: [0x00,0x22,0x3c,0xd5]
+// CHECK: msr VNCR_EL2, x0 // encoding: [0x00,0x22,0x1c,0xd5]
+
+//CHECK-NO-V84: error: expected readable system register
+//CHECK-NO-V84-NEXT: mrs x0, VNCR_EL2
+//CHECK-NO-V84-NEXT: ^
+//CHECK-NO-V84-NEXT: error: expected writable system register or pstate
+//CHECK-NO-V84-NEXT: msr VNCR_EL2, x0
+//CHECK-NO-V84-NEXT: ^
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt Tue Jul 3 05:09:20 2018
@@ -0,0 +1,277 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x00,0xd2,0x1b,0xd5]
+[0x60,0xd2,0x1b,0xd5]
+[0x80,0xd2,0x1b,0xd5]
+[0xa0,0xd2,0x1b,0xd5]
+[0x00,0xd4,0x1b,0xd5]
+[0x20,0xd4,0x1b,0xd5]
+[0x40,0xd4,0x1b,0xd5]
+[0x60,0xd4,0x1b,0xd5]
+[0x00,0xd3,0x1b,0xd5]
+[0x20,0xd3,0x1b,0xd5]
+[0x00,0xdc,0x1b,0xd5]
+[0x20,0xdc,0x1b,0xd5]
+[0x40,0xdc,0x1b,0xd5]
+[0x60,0xdc,0x1b,0xd5]
+[0x80,0xdc,0x1b,0xd5]
+[0xa0,0xdc,0x1b,0xd5]
+[0xc0,0xdc,0x1b,0xd5]
+[0xe0,0xdc,0x1b,0xd5]
+[0x00,0xdd,0x1b,0xd5]
+[0x20,0xdd,0x1b,0xd5]
+[0x40,0xdd,0x1b,0xd5]
+[0x60,0xdd,0x1b,0xd5]
+[0x80,0xdd,0x1b,0xd5]
+[0xa0,0xdd,0x1b,0xd5]
+[0xc0,0xdd,0x1b,0xd5]
+[0xe0,0xdd,0x1b,0xd5]
+[0x00,0xde,0x1b,0xd5]
+[0x20,0xde,0x1b,0xd5]
+[0x40,0xde,0x1b,0xd5]
+[0x60,0xde,0x1b,0xd5]
+[0x80,0xde,0x1b,0xd5]
+[0xa0,0xde,0x1b,0xd5]
+[0xc0,0xde,0x1b,0xd5]
+[0xe0,0xde,0x1b,0xd5]
+[0x00,0xdf,0x1b,0xd5]
+[0x20,0xdf,0x1b,0xd5]
+[0x40,0xdf,0x1b,0xd5]
+[0x60,0xdf,0x1b,0xd5]
+[0x80,0xdf,0x1b,0xd5]
+[0xa0,0xdf,0x1b,0xd5]
+[0xc0,0xdf,0x1b,0xd5]
+[0xe0,0xdf,0x1b,0xd5]
+
+[0x00,0xd2,0x3b,0xd5]
+[0x20,0xd2,0x3b,0xd5]
+[0x40,0xd2,0x3b,0xd5]
+[0x60,0xd2,0x3b,0xd5]
+[0x80,0xd2,0x3b,0xd5]
+[0xa0,0xd2,0x3b,0xd5]
+[0x00,0xd4,0x3b,0xd5]
+[0x20,0xd4,0x3b,0xd5]
+[0x40,0xd4,0x3b,0xd5]
+[0x60,0xd4,0x3b,0xd5]
+[0x00,0xd6,0x3b,0xd5]
+[0x20,0xd6,0x3b,0xd5]
+[0x40,0xd6,0x3b,0xd5]
+[0x60,0xd6,0x3b,0xd5]
+[0x00,0xd3,0x3b,0xd5]
+[0x20,0xd3,0x3b,0xd5]
+[0x00,0xdc,0x3b,0xd5]
+[0x20,0xdc,0x3b,0xd5]
+[0x40,0xdc,0x3b,0xd5]
+[0x60,0xdc,0x3b,0xd5]
+[0x80,0xdc,0x3b,0xd5]
+[0xa0,0xdc,0x3b,0xd5]
+[0xc0,0xdc,0x3b,0xd5]
+[0xe0,0xdc,0x3b,0xd5]
+[0x00,0xdd,0x3b,0xd5]
+[0x20,0xdd,0x3b,0xd5]
+[0x40,0xdd,0x3b,0xd5]
+[0x60,0xdd,0x3b,0xd5]
+[0x80,0xdd,0x3b,0xd5]
+[0xa0,0xdd,0x3b,0xd5]
+[0xc0,0xdd,0x3b,0xd5]
+[0xe0,0xdd,0x3b,0xd5]
+[0x00,0xde,0x3b,0xd5]
+[0x20,0xde,0x3b,0xd5]
+[0x40,0xde,0x3b,0xd5]
+[0x60,0xde,0x3b,0xd5]
+[0x80,0xde,0x3b,0xd5]
+[0xa0,0xde,0x3b,0xd5]
+[0xc0,0xde,0x3b,0xd5]
+[0xe0,0xde,0x3b,0xd5]
+[0x00,0xdf,0x3b,0xd5]
+[0x20,0xdf,0x3b,0xd5]
+[0x40,0xdf,0x3b,0xd5]
+[0x60,0xdf,0x3b,0xd5]
+[0x80,0xdf,0x3b,0xd5]
+[0xa0,0xdf,0x3b,0xd5]
+[0xc0,0xdf,0x3b,0xd5]
+[0xe0,0xdf,0x3b,0xd5]
+
+#CHECK: msr AMCR_EL0, x0
+#CHECK: msr AMUSERENR_EL0, x0
+#CHECK: msr AMCNTENCLR0_EL0, x0
+#CHECK: msr AMCNTENSET0_EL0, x0
+#CHECK: msr AMEVCNTR00_EL0, x0
+#CHECK: msr AMEVCNTR01_EL0, x0
+#CHECK: msr AMEVCNTR02_EL0, x0
+#CHECK: msr AMEVCNTR03_EL0, x0
+#CHECK: msr AMCNTENCLR1_EL0, x0
+#CHECK: msr AMCNTENSET1_EL0, x0
+#CHECK: msr AMEVCNTR10_EL0, x0
+#CHECK: msr AMEVCNTR11_EL0, x0
+#CHECK: msr AMEVCNTR12_EL0, x0
+#CHECK: msr AMEVCNTR13_EL0, x0
+#CHECK: msr AMEVCNTR14_EL0, x0
+#CHECK: msr AMEVCNTR15_EL0, x0
+#CHECK: msr AMEVCNTR16_EL0, x0
+#CHECK: msr AMEVCNTR17_EL0, x0
+#CHECK: msr AMEVCNTR18_EL0, x0
+#CHECK: msr AMEVCNTR19_EL0, x0
+#CHECK: msr AMEVCNTR110_EL0, x0
+#CHECK: msr AMEVCNTR111_EL0, x0
+#CHECK: msr AMEVCNTR112_EL0, x0
+#CHECK: msr AMEVCNTR113_EL0, x0
+#CHECK: msr AMEVCNTR114_EL0, x0
+#CHECK: msr AMEVCNTR115_EL0, x0
+#CHECK: msr AMEVTYPER10_EL0, x0
+#CHECK: msr AMEVTYPER11_EL0, x0
+#CHECK: msr AMEVTYPER12_EL0, x0
+#CHECK: msr AMEVTYPER13_EL0, x0
+#CHECK: msr AMEVTYPER14_EL0, x0
+#CHECK: msr AMEVTYPER15_EL0, x0
+#CHECK: msr AMEVTYPER16_EL0, x0
+#CHECK: msr AMEVTYPER17_EL0, x0
+#CHECK: msr AMEVTYPER18_EL0, x0
+#CHECK: msr AMEVTYPER19_EL0, x0
+#CHECK: msr AMEVTYPER110_EL0, x0
+#CHECK: msr AMEVTYPER111_EL0, x0
+#CHECK: msr AMEVTYPER112_EL0, x0
+#CHECK: msr AMEVTYPER113_EL0, x0
+#CHECK: msr AMEVTYPER114_EL0, x0
+#CHECK: msr AMEVTYPER115_EL0, x0
+
+#CHECK: mrs x0, AMCR_EL0
+#CHECK: mrs x0, AMCFGR_EL0
+#CHECK: mrs x0, AMCGCR_EL0
+#CHECK: mrs x0, AMUSERENR_EL0
+#CHECK: mrs x0, AMCNTENCLR0_EL0
+#CHECK: mrs x0, AMCNTENSET0_EL0
+#CHECK: mrs x0, AMEVCNTR00_EL0
+#CHECK: mrs x0, AMEVCNTR01_EL0
+#CHECK: mrs x0, AMEVCNTR02_EL0
+#CHECK: mrs x0, AMEVCNTR03_EL0
+#CHECK: mrs x0, AMEVTYPER00_EL0
+#CHECK: mrs x0, AMEVTYPER01_EL0
+#CHECK: mrs x0, AMEVTYPER02_EL0
+#CHECK: mrs x0, AMEVTYPER03_EL0
+#CHECK: mrs x0, AMCNTENCLR1_EL0
+#CHECK: mrs x0, AMCNTENSET1_EL0
+#CHECK: mrs x0, AMEVCNTR10_EL0
+#CHECK: mrs x0, AMEVCNTR11_EL0
+#CHECK: mrs x0, AMEVCNTR12_EL0
+#CHECK: mrs x0, AMEVCNTR13_EL0
+#CHECK: mrs x0, AMEVCNTR14_EL0
+#CHECK: mrs x0, AMEVCNTR15_EL0
+#CHECK: mrs x0, AMEVCNTR16_EL0
+#CHECK: mrs x0, AMEVCNTR17_EL0
+#CHECK: mrs x0, AMEVCNTR18_EL0
+#CHECK: mrs x0, AMEVCNTR19_EL0
+#CHECK: mrs x0, AMEVCNTR110_EL0
+#CHECK: mrs x0, AMEVCNTR111_EL0
+#CHECK: mrs x0, AMEVCNTR112_EL0
+#CHECK: mrs x0, AMEVCNTR113_EL0
+#CHECK: mrs x0, AMEVCNTR114_EL0
+#CHECK: mrs x0, AMEVCNTR115_EL0
+#CHECK: mrs x0, AMEVTYPER10_EL0
+#CHECK: mrs x0, AMEVTYPER11_EL0
+#CHECK: mrs x0, AMEVTYPER12_EL0
+#CHECK: mrs x0, AMEVTYPER13_EL0
+#CHECK: mrs x0, AMEVTYPER14_EL0
+#CHECK: mrs x0, AMEVTYPER15_EL0
+#CHECK: mrs x0, AMEVTYPER16_EL0
+#CHECK: mrs x0, AMEVTYPER17_EL0
+#CHECK: mrs x0, AMEVTYPER18_EL0
+#CHECK: mrs x0, AMEVTYPER19_EL0
+#CHECK: mrs x0, AMEVTYPER110_EL0
+#CHECK: mrs x0, AMEVTYPER111_EL0
+#CHECK: mrs x0, AMEVTYPER112_EL0
+#CHECK: mrs x0, AMEVTYPER113_EL0
+#CHECK: mrs x0, AMEVTYPER114_EL0
+#CHECK: mrs x0, AMEVTYPER115_EL0
+
+#CHECK-NO-V84: msr S3_3_C13_C2_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C2_3, x0
+#CHECK-NO-V84: msr S3_3_C13_C2_4, x0
+#CHECK-NO-V84: msr S3_3_C13_C2_5, x0
+#CHECK-NO-V84: msr S3_3_C13_C4_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C4_1, x0
+#CHECK-NO-V84: msr S3_3_C13_C4_2, x0
+#CHECK-NO-V84: msr S3_3_C13_C4_3, x0
+#CHECK-NO-V84: msr S3_3_C13_C3_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C3_1, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_1, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_2, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_3, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_4, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_5, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_6, x0
+#CHECK-NO-V84: msr S3_3_C13_C12_7, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_1, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_2, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_3, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_4, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_5, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_6, x0
+#CHECK-NO-V84: msr S3_3_C13_C13_7, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_1, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_2, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_3, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_4, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_5, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_6, x0
+#CHECK-NO-V84: msr S3_3_C13_C14_7, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_0, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_1, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_2, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_3, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_4, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_5, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_6, x0
+#CHECK-NO-V84: msr S3_3_C13_C15_7, x0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C2_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C2_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C2_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C2_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C2_4
+#CHECK-NO-V84: mrs x0, S3_3_C13_C2_5
+#CHECK-NO-V84: mrs x0, S3_3_C13_C4_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C4_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C4_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C4_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C6_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C6_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C6_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C6_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C3_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C3_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_4
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_5
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_6
+#CHECK-NO-V84: mrs x0, S3_3_C13_C12_7
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_4
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_5
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_6
+#CHECK-NO-V84: mrs x0, S3_3_C13_C13_7
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_4
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_5
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_6
+#CHECK-NO-V84: mrs x0, S3_3_C13_C14_7
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_0
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_1
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_2
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_3
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_4
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_5
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_6
+#CHECK-NO-V84: mrs x0, S3_3_C13_C15_7
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-dit.txt?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-dit.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-dit.txt Tue Jul 3 05:09:20 2018
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x5f,0x41,0x03,0xd5]
+[0xa0,0x42,0x1b,0xd5]
+[0xa0,0x42,0x3b,0xd5]
+
+#CHECK: msr DIT, #1
+#CHECK: msr DIT, x0
+#CHECK: mrs x0, DIT
+
+#CHECK-NO-V84: msr S0_3_C4_C1_2, xzr
+#CHECK-NO-V84: msr S3_3_C4_C2_5, x0
+#CHECK-NO-V84: mrs x0, S3_3_C4_C2_5
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt Tue Jul 3 05:09:20 2018
@@ -0,0 +1,99 @@
+#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s | FileCheck %s --check-prefix=CHECK-NOV84
+
+[0x20,0xa5,0x18,0xd5]
+[0x00,0xa5,0x18,0xd5]
+[0x00,0xa5,0x1c,0xd5]
+[0x00,0xa5,0x1e,0xd5]
+[0x00,0xa5,0x1d,0xd5]
+[0x00,0xa4,0x1c,0xd5]
+[0x20,0xa4,0x1c,0xd5]
+[0x00,0xa6,0x1c,0xd5]
+[0x20,0xa6,0x1c,0xd5]
+[0x40,0xa6,0x1c,0xd5]
+[0x60,0xa6,0x1c,0xd5]
+[0x80,0xa6,0x1c,0xd5]
+[0xa0,0xa6,0x1c,0xd5]
+[0xc0,0xa6,0x1c,0xd5]
+[0xe0,0xa6,0x1c,0xd5]
+[0x20,0xa5,0x38,0xd5]
+[0x00,0xa5,0x38,0xd5]
+[0x00,0xa5,0x3c,0xd5]
+[0x00,0xa5,0x3e,0xd5]
+[0x00,0xa5,0x3d,0xd5]
+[0x00,0xa4,0x3c,0xd5]
+[0x20,0xa4,0x3c,0xd5]
+[0x00,0xa6,0x3c,0xd5]
+[0x20,0xa6,0x3c,0xd5]
+[0x40,0xa6,0x3c,0xd5]
+[0x60,0xa6,0x3c,0xd5]
+[0x80,0xa6,0x3c,0xd5]
+[0xa0,0xa6,0x3c,0xd5]
+[0xc0,0xa6,0x3c,0xd5]
+[0xe0,0xa6,0x3c,0xd5]
+[0x80,0xa4,0x38,0xd5]
+
+#CHECK: msr MPAM0_EL1, x0
+#CHECK: msr MPAM1_EL1, x0
+#CHECK: msr MPAM2_EL2, x0
+#CHECK: msr MPAM3_EL3, x0
+#CHECK: msr MPAM1_EL12, x0
+#CHECK: msr MPAMHCR_EL2, x0
+#CHECK: msr MPAMVPMV_EL2, x0
+#CHECK: msr MPAMVPM0_EL2, x0
+#CHECK: msr MPAMVPM1_EL2, x0
+#CHECK: msr MPAMVPM2_EL2, x0
+#CHECK: msr MPAMVPM3_EL2, x0
+#CHECK: msr MPAMVPM4_EL2, x0
+#CHECK: msr MPAMVPM5_EL2, x0
+#CHECK: msr MPAMVPM6_EL2, x0
+#CHECK: msr MPAMVPM7_EL2, x0
+#CHECK: mrs x0, MPAM0_EL1
+#CHECK: mrs x0, MPAM1_EL1
+#CHECK: mrs x0, MPAM2_EL2
+#CHECK: mrs x0, MPAM3_EL3
+#CHECK: mrs x0, MPAM1_EL12
+#CHECK: mrs x0, MPAMHCR_EL2
+#CHECK: mrs x0, MPAMVPMV_EL2
+#CHECK: mrs x0, MPAMVPM0_EL2
+#CHECK: mrs x0, MPAMVPM1_EL2
+#CHECK: mrs x0, MPAMVPM2_EL2
+#CHECK: mrs x0, MPAMVPM3_EL2
+#CHECK: mrs x0, MPAMVPM4_EL2
+#CHECK: mrs x0, MPAMVPM5_EL2
+#CHECK: mrs x0, MPAMVPM6_EL2
+#CHECK: mrs x0, MPAMVPM7_EL2
+#CHECK: mrs x0, MPAMIDR_EL1
+
+#CHECK-NOV84: msr S3_0_C10_C5_1, x0
+#CHECK-NOV84: msr S3_0_C10_C5_0, x0
+#CHECK-NOV84: msr S3_4_C10_C5_0, x0
+#CHECK-NOV84: msr S3_6_C10_C5_0, x0
+#CHECK-NOV84: msr S3_5_C10_C5_0, x0
+#CHECK-NOV84: msr S3_4_C10_C4_0, x0
+#CHECK-NOV84: msr S3_4_C10_C4_1, x0
+#CHECK-NOV84: msr S3_4_C10_C6_0, x0
+#CHECK-NOV84: msr S3_4_C10_C6_1, x0
+#CHECK-NOV84: msr S3_4_C10_C6_2, x0
+#CHECK-NOV84: msr S3_4_C10_C6_3, x0
+#CHECK-NOV84: msr S3_4_C10_C6_4, x0
+#CHECK-NOV84: msr S3_4_C10_C6_5, x0
+#CHECK-NOV84: msr S3_4_C10_C6_6, x0
+#CHECK-NOV84: msr S3_4_C10_C6_7, x0
+#CHECK-NOV84: mrs x0, S3_0_C10_C5_1
+#CHECK-NOV84: mrs x0, S3_0_C10_C5_0
+#CHECK-NOV84: mrs x0, S3_4_C10_C5_0
+#CHECK-NOV84: mrs x0, S3_6_C10_C5_0
+#CHECK-NOV84: mrs x0, S3_5_C10_C5_0
+#CHECK-NOV84: mrs x0, S3_4_C10_C4_0
+#CHECK-NOV84: mrs x0, S3_4_C10_C4_1
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_0
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_1
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_2
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_3
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_4
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_5
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_6
+#CHECK-NOV84: mrs x0, S3_4_C10_C6_7
+#CHECK-NOV84: mrs x0, S3_0_C10_C4_4
+
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-ras.txt?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-ras.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-ras.txt Tue Jul 3 05:09:20 2018
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+
+0xa0,0x54,0x18,0xd5
+0xa0,0x54,0x38,0xd5
+0xc0,0x54,0x18,0xd5
+0xc0,0x54,0x38,0xd5
+0xe0,0x55,0x18,0xd5
+0xe0,0x55,0x38,0xd5
+0x80,0x54,0x38,0xd5
+
+0x40,0x55,0x18,0xd5
+0x40,0x55,0x38,0xd5
+0x60,0x55,0x18,0xd5
+0x60,0x55,0x38,0xd5
+
+#CHECK: msr ERXPFGCTL_EL1, x0
+#CHECK: mrs x0, ERXPFGCTL_EL1
+#CHECK: msr ERXPFGCDN_EL1, x0
+#CHECK: mrs x0, ERXPFGCDN_EL1
+#CHECK: msr ERXTS_EL1, x0
+#CHECK: mrs x0, ERXTS_EL1
+#CHECK: mrs x0, ERXPFGF_EL1
+
+#CHECK: msr ERXMISC2_EL1, x0
+#CHECK: mrs x0, ERXMISC2_EL1
+#CHECK: msr ERXMISC3_EL1, x0
+#CHECK: mrs x0, ERXMISC3_EL1
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-trace.txt?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-trace.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-trace.txt Tue Jul 3 05:09:20 2018
@@ -0,0 +1,23 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x20,0x12,0x18,0xd5]
+[0x20,0x12,0x1c,0xd5]
+[0x20,0x12,0x1d,0xd5]
+[0x20,0x12,0x38,0xd5]
+[0x20,0x12,0x3c,0xd5]
+[0x20,0x12,0x3d,0xd5]
+
+#CHECK: msr TRFCR_EL1, x0
+#CHECK: msr TRFCR_EL2, x0
+#CHECK: msr TRFCR_EL12, x0
+#CHECK: mrs x0, TRFCR_EL1
+#CHECK: mrs x0, TRFCR_EL2
+#CHECK: mrs x0, TRFCR_EL12
+
+#CHECK-NO-V84: msr S3_0_C1_C2_1, x0
+#CHECK-NO-V84: msr S3_4_C1_C2_1, x0
+#CHECK-NO-V84: msr S3_5_C1_C2_1, x0
+#CHECK-NO-V84: mrs x0, S3_0_C1_C2_1
+#CHECK-NO-V84: mrs x0, S3_4_C1_C2_1
+#CHECK-NO-V84: mrs x0, S3_5_C1_C2_1
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt?rev=336193&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt Tue Jul 3 05:09:20 2018
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x00,0x22,0x3c,0xd5]
+[0x00,0x22,0x1c,0xd5]
+
+# CHECK: mrs x0, VNCR_EL2
+# CHECK: msr VNCR_EL2, x0
+
+# CHECK-NO-V84: mrs x0, S3_4_C2_C2_0
+# CHECK-NO-V84: msr S3_4_C2_C2_0, x0
More information about the llvm-commits
mailing list