[PATCH] D48869: [AArch64][SVE] Asm: Support for SVE condition code aliases

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2506
   AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower())
-                    .Case("eq", AArch64CC::EQ)
-                    .Case("ne", AArch64CC::NE)
-                    .Case("cs", AArch64CC::HS)
-                    .Case("hs", AArch64CC::HS)
-                    .Case("cc", AArch64CC::LO)
-                    .Case("lo", AArch64CC::LO)
-                    .Case("mi", AArch64CC::MI)
-                    .Case("pl", AArch64CC::PL)
-                    .Case("vs", AArch64CC::VS)
-                    .Case("vc", AArch64CC::VC)
-                    .Case("hi", AArch64CC::HI)
-                    .Case("ls", AArch64CC::LS)
-                    .Case("ge", AArch64CC::GE)
-                    .Case("lt", AArch64CC::LT)
-                    .Case("gt", AArch64CC::GT)
-                    .Case("le", AArch64CC::LE)
-                    .Case("al", AArch64CC::AL)
-                    .Case("nv", AArch64CC::NV)
+                    .Case("eq",    AArch64CC::EQ)
+                    .Case("ne",    AArch64CC::NE)
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I just realise there is an unnecessary whitespace change here that someone will surely comment on :) I'll remove that before committing.


https://reviews.llvm.org/D48869