[llvm] r336182 - [AArch64][SVE] Asm: Support for vector element FP compare.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 3 02:07:23 PDT 2018
Author: s.desmalen
Date: Tue Jul 3 02:07:23 2018
New Revision: 336182
URL: http://llvm.org/viewvc/llvm-project?rev=336182&view=rev
Log:
[AArch64][SVE] Asm: Support for vector element FP compare.
Contains the following variants:
- Compare with (elements from) other vector
instructions: fcmeq, fcmgt, fcmge, fcmne, fcmuo.
aliases: fcmle, fcmlt.
e.g. fcmle p0.h, p0/z, z0.h, z1.h => fcmge p0.h, p0/z, z1.h, z0.h
- Compare absolute values with (absolute values from) other vector.
instructions: facge, facgt.
aliases: facle, faclt.
e.g. facle p0.h, p0/z, z0.h, z1.h => facge p0.h, p0/z, z1.h, z0.h
- Compare vector elements with #0.0
instructions: fcmeq, fcmgt, fcmge, fcmle, fcmlt, fcmne.
e.g. fcmle p0.h, p0/z, z0.h, #0.0
Added:
llvm/trunk/test/MC/AArch64/SVE/facge-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/facge.s
llvm/trunk/test/MC/AArch64/SVE/facgt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/facgt.s
llvm/trunk/test/MC/AArch64/SVE/facle-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/facle.s
llvm/trunk/test/MC/AArch64/SVE/faclt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/faclt.s
llvm/trunk/test/MC/AArch64/SVE/fcmeq-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmeq.s
llvm/trunk/test/MC/AArch64/SVE/fcmge-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmge.s
llvm/trunk/test/MC/AArch64/SVE/fcmgt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmgt.s
llvm/trunk/test/MC/AArch64/SVE/fcmle-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmle.s
llvm/trunk/test/MC/AArch64/SVE/fcmlt-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmlt.s
llvm/trunk/test/MC/AArch64/SVE/fcmne-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmne.s
llvm/trunk/test/MC/AArch64/SVE/fcmuo-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fcmuo.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=336182&r1=336181&r2=336182&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Tue Jul 3 02:07:23 2018
@@ -538,6 +538,21 @@ let Predicates = [HasSVE] in {
defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo">;
defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls">;
+ defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge">;
+ defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt">;
+ defm FCMEQ_PPzZZ : sve_fp_3op_p_pd<0b010, "fcmeq">;
+ defm FCMNE_PPzZZ : sve_fp_3op_p_pd<0b011, "fcmne">;
+ defm FCMUO_PPzZZ : sve_fp_3op_p_pd<0b100, "fcmuo">;
+ defm FACGE_PPzZZ : sve_fp_3op_p_pd<0b101, "facge">;
+ defm FACGT_PPzZZ : sve_fp_3op_p_pd<0b111, "facgt">;
+
+ defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge">;
+ defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt">;
+ defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt">;
+ defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle">;
+ defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq">;
+ defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne">;
+
defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">;
defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">;
defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">;
@@ -678,4 +693,32 @@ let Predicates = [HasSVE] in {
(CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
(CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+ def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
+ (FACGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+ def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
+ (FACGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+ def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
+ (FACGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+ def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
+ (FACGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+ def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
+ (FACGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+ def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
+ (FACGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+ def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
+ (FCMGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+ def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
+ (FCMGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+ def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
+ (FCMGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+ def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
+ (FCMGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+ def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
+ (FCMGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+ def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
+ (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
}
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=336182&r1=336181&r2=336182&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Tue Jul 3 02:07:23 2018
@@ -3381,7 +3381,7 @@ bool AArch64AsmParser::parseOperand(Oper
uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
if (Mnemonic != "fcmp" && Mnemonic != "fcmpe" && Mnemonic != "fcmeq" &&
Mnemonic != "fcmge" && Mnemonic != "fcmgt" && Mnemonic != "fcmle" &&
- Mnemonic != "fcmlt")
+ Mnemonic != "fcmlt" && Mnemonic != "fcmne")
return TokError("unexpected floating point literal");
else if (IntVal != 0 || isNegative)
return TokError("expected floating-point constant #0.0");
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=336182&r1=336181&r2=336182&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Tue Jul 3 02:07:23 2018
@@ -1232,6 +1232,71 @@ multiclass sve_int_ucmp_vi<bits<2> opc,
//===----------------------------------------------------------------------===//
+// SVE Floating Point Compare - Vectors Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
+ ZPRRegOp zprty>
+: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+ asm, "\t$Pd, $Pg/z, $Zn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<4> Pd;
+ bits<3> Pg;
+ bits<5> Zm;
+ bits<5> Zn;
+ let Inst{31-24} = 0b01100101;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b0;
+ let Inst{20-16} = Zm;
+ let Inst{15} = opc{2};
+ let Inst{14} = 0b1;
+ let Inst{13} = opc{1};
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4} = opc{0};
+ let Inst{3-0} = Pd;
+}
+
+multiclass sve_fp_3op_p_pd<bits<3> opc, string asm> {
+ def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
+ def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
+ def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
+}
+
+
+//===----------------------------------------------------------------------===//
+// SVE Floating Point Compare - with Zero Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
+ ZPRRegOp zprty>
+: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn),
+ asm, "\t$Pd, $Pg/z, $Zn, #0.0",
+ "",
+ []>, Sched<[]> {
+ bits<4> Pd;
+ bits<3> Pg;
+ bits<5> Zn;
+ let Inst{31-24} = 0b01100101;
+ let Inst{23-22} = sz;
+ let Inst{21-18} = 0b0100;
+ let Inst{17-16} = opc{2-1};
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4} = opc{0};
+ let Inst{3-0} = Pd;
+}
+
+multiclass sve_fp_2op_p_pd<bits<3> opc, string asm> {
+ def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
+ def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
+ def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
+}
+
+
+//===----------------------------------------------------------------------===//
//SVE Index Generation Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE/facge-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/facge-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/facge-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/facge-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+facge p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: facge p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+facge p0.b, p0/z, z0.b, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
+// CHECK-NEXT: facge p0.b, p0/z, z0.b, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/facge.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/facge.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/facge.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/facge.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+facge p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: facge p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x10,0xc0,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 c0 41 65 <unknown>
+
+facge p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: facge p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x10,0xc0,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 c0 81 65 <unknown>
+
+facge p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: facge p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x10,0xc0,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 c0 c1 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/facgt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/facgt-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/facgt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/facgt-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+facgt p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: facgt p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+facgt p0.b, p0/z, z0.b, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
+// CHECK-NEXT: facgt p0.b, p0/z, z0.b, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/facgt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/facgt.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/facgt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/facgt.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+facgt p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: facgt p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x10,0xe0,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 e0 41 65 <unknown>
+
+facgt p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: facgt p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x10,0xe0,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 e0 81 65 <unknown>
+
+facgt p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: facgt p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x10,0xe0,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 e0 c1 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/facle-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/facle-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/facle-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/facle-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+facle p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: facle p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+facle p0.b, p0/z, z0.b, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
+// CHECK-NEXT: facle p0.b, p0/z, z0.b, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/facle.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/facle.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/facle.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/facle.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+facle p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: facge p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x30,0xc0,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 c0 40 65 <unknown>
+
+facle p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: facge p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x30,0xc0,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 c0 80 65 <unknown>
+
+facle p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: facge p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x30,0xc0,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 c0 c0 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/faclt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/faclt-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/faclt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/faclt-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+faclt p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: faclt p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+faclt p0.b, p0/z, z0.b, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
+// CHECK-NEXT: faclt p0.b, p0/z, z0.b, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/faclt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/faclt.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/faclt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/faclt.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+faclt p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: facgt p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x30,0xe0,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 e0 40 65 <unknown>
+
+faclt p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: facgt p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x30,0xe0,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 e0 80 65 <unknown>
+
+faclt p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: facgt p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x30,0xe0,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 e0 c0 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmeq-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmeq-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmeq-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmeq-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmeq p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmeq p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmeq p0.s, p0/z, z0.s, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
+// CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmeq.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmeq.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmeq.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmeq.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmeq p0.h, p0/z, z0.h, #0.0
+// CHECK-INST: fcmeq p0.h, p0/z, z0.h, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x52,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 52 65 <unknown>
+
+fcmeq p0.s, p0/z, z0.s, #0.0
+// CHECK-INST: fcmeq p0.s, p0/z, z0.s, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x92,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 92 65 <unknown>
+
+fcmeq p0.d, p0/z, z0.d, #0.0
+// CHECK-INST: fcmeq p0.d, p0/z, z0.d, #0.0
+// CHECK-ENCODING: [0x00,0x20,0xd2,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 d2 65 <unknown>
+
+fcmeq p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmeq p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x00,0x60,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 41 65 <unknown>
+
+fcmeq p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmeq p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x00,0x60,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 81 65 <unknown>
+
+fcmeq p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmeq p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x00,0x60,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 c1 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmge-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmge-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmge-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmge-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmge p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmge p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmge p0.s, p0/z, z0.s, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
+// CHECK-NEXT: fcmge p0.s, p0/z, z0.s, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmge.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmge.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmge.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmge.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmge p0.h, p0/z, z0.h, #0.0
+// CHECK-INST: fcmge p0.h, p0/z, z0.h, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x50,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 50 65 <unknown>
+
+fcmge p0.s, p0/z, z0.s, #0.0
+// CHECK-INST: fcmge p0.s, p0/z, z0.s, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x90,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 90 65 <unknown>
+
+fcmge p0.d, p0/z, z0.d, #0.0
+// CHECK-INST: fcmge p0.d, p0/z, z0.d, #0.0
+// CHECK-ENCODING: [0x00,0x20,0xd0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 d0 65 <unknown>
+
+fcmge p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmge p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x00,0x40,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 41 65 <unknown>
+
+fcmge p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmge p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x00,0x40,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 81 65 <unknown>
+
+fcmge p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmge p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x00,0x40,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c1 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmgt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmgt-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmgt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmgt-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmgt p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmgt p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmgt p0.s, p0/z, z0.s, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
+// CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmgt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmgt.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmgt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmgt.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmgt p0.h, p0/z, z0.h, #0.0
+// CHECK-INST: fcmgt p0.h, p0/z, z0.h, #0.0
+// CHECK-ENCODING: [0x10,0x20,0x50,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 50 65 <unknown>
+
+fcmgt p0.s, p0/z, z0.s, #0.0
+// CHECK-INST: fcmgt p0.s, p0/z, z0.s, #0.0
+// CHECK-ENCODING: [0x10,0x20,0x90,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 90 65 <unknown>
+
+fcmgt p0.d, p0/z, z0.d, #0.0
+// CHECK-INST: fcmgt p0.d, p0/z, z0.d, #0.0
+// CHECK-ENCODING: [0x10,0x20,0xd0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 d0 65 <unknown>
+
+fcmgt p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmgt p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x10,0x40,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 41 65 <unknown>
+
+fcmgt p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmgt p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x10,0x40,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 81 65 <unknown>
+
+fcmgt p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmgt p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x10,0x40,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 c1 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmle-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmle-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmle-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmle-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmle p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmle p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmle p0.s, p0/z, z0.s, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
+// CHECK-NEXT: fcmle p0.s, p0/z, z0.s, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmle.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmle.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmle.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmle.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmle p0.h, p0/z, z0.h, #0.0
+// CHECK-INST: fcmle p0.h, p0/z, z0.h, #0.0
+// CHECK-ENCODING: [0x10,0x20,0x51,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 51 65 <unknown>
+
+fcmle p0.s, p0/z, z0.s, #0.0
+// CHECK-INST: fcmle p0.s, p0/z, z0.s, #0.0
+// CHECK-ENCODING: [0x10,0x20,0x91,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 91 65 <unknown>
+
+fcmle p0.d, p0/z, z0.d, #0.0
+// CHECK-INST: fcmle p0.d, p0/z, z0.d, #0.0
+// CHECK-ENCODING: [0x10,0x20,0xd1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 d1 65 <unknown>
+
+fcmle p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmge p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x20,0x40,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 40 40 65 <unknown>
+
+fcmle p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmge p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x20,0x40,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 40 80 65 <unknown>
+
+fcmle p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmge p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x20,0x40,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 40 c0 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmlt-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmlt-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmlt-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmlt-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmlt p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmlt p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmlt p0.s, p0/z, z0.s, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
+// CHECK-NEXT: fcmlt p0.s, p0/z, z0.s, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmlt.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmlt.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmlt.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmlt.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmlt p0.h, p0/z, z0.h, #0.0
+// CHECK-INST: fcmlt p0.h, p0/z, z0.h, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x51,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 51 65 <unknown>
+
+fcmlt p0.s, p0/z, z0.s, #0.0
+// CHECK-INST: fcmlt p0.s, p0/z, z0.s, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x91,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 91 65 <unknown>
+
+fcmlt p0.d, p0/z, z0.d, #0.0
+// CHECK-INST: fcmlt p0.d, p0/z, z0.d, #0.0
+// CHECK-ENCODING: [0x00,0x20,0xd1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 d1 65 <unknown>
+
+fcmlt p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmgt p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x30,0x40,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 40 40 65 <unknown>
+
+fcmlt p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmgt p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x30,0x40,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 40 80 65 <unknown>
+
+fcmlt p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmgt p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x30,0x40,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 40 c0 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmne-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmne-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmne-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmne-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmne p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmne p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmne p0.s, p0/z, z0.s, #1.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0
+// CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #1.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmne.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmne.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmne.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmne.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmne p0.h, p0/z, z0.h, #0.0
+// CHECK-INST: fcmne p0.h, p0/z, z0.h, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x53,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 53 65 <unknown>
+
+fcmne p0.s, p0/z, z0.s, #0.0
+// CHECK-INST: fcmne p0.s, p0/z, z0.s, #0.0
+// CHECK-ENCODING: [0x00,0x20,0x93,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 93 65 <unknown>
+
+fcmne p0.d, p0/z, z0.d, #0.0
+// CHECK-INST: fcmne p0.d, p0/z, z0.d, #0.0
+// CHECK-ENCODING: [0x00,0x20,0xd3,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 d3 65 <unknown>
+
+fcmne p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmne p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x10,0x60,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 60 41 65 <unknown>
+
+fcmne p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmne p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x10,0x60,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 60 81 65 <unknown>
+
+fcmne p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmne p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x10,0x60,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 60 c1 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/fcmuo-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmuo-diagnostics.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmuo-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmuo-diagnostics.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fcmuo p0.b, p0/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: fcmuo p0.b, p0/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcmuo p0.s, p0/z, z0.s, #0.0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
+// CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, #0.0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/fcmuo.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fcmuo.s?rev=336182&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fcmuo.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/fcmuo.s Tue Jul 3 02:07:23 2018
@@ -0,0 +1,27 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fcmuo p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: fcmuo p0.h, p0/z, z0.h, z1.h
+// CHECK-ENCODING: [0x00,0xc0,0x41,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 41 65 <unknown>
+
+fcmuo p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: fcmuo p0.s, p0/z, z0.s, z1.s
+// CHECK-ENCODING: [0x00,0xc0,0x81,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 81 65 <unknown>
+
+fcmuo p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: fcmuo p0.d, p0/z, z0.d, z1.d
+// CHECK-ENCODING: [0x00,0xc0,0xc1,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 c1 65 <unknown>
+
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