[PATCH] D48846: [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.

[Vadzim Dambrouski via Phabricator via llvm-commits]

pftbest created this revision.
pftbest added reviewers: efriedma, rogfer01.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, chrib, kristof.beyls.

Repository:
  rL LLVM

https://reviews.llvm.org/D48846

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/overflow-intrinsic-optimizations.ll


Index: test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
===================================================================
--- test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
+++ test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK-V6M-THUMB
 
 define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: sadd:
@@ -81,6 +82,7 @@
 ; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
 ; CHECK-NEXT: cmp r[[RHI]], r0, asr #31
 ; CHECK-NEXT: moveq pc, lr
+; CHECK-V6M-THUMB-NOT: smull
 entry:
   %0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1
@@ -100,6 +102,7 @@
 ; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
 ; CHECK-NEXT: cmp r[[RHI]], #0
 ; CHECK-NEXT: moveq pc, lr
+; CHECK-V6M-THUMB-NOT: umull
 entry:
   %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -4681,9 +4681,11 @@
   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
   // instruction.
   unsigned Opc = Cond.getOpcode();
+  bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+                      !Subtarget->isThumb1Only();
   if (Cond.getResNo() == 1 &&
       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
-       Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
+       Opc == ISD::USUBO || OptimizeMul)) {
     // Only lower legal XALUO ops.
     if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
       return SDValue();
@@ -4730,9 +4732,11 @@
   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
   // instruction.
   unsigned Opc = LHS.getOpcode();
+  bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+                      !Subtarget->isThumb1Only();
   if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
-       Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+       Opc == ISD::USUBO || OptimizeMul) &&
       (CC == ISD::SETEQ || CC == ISD::SETNE)) {
     // Only lower legal XALUO ops.
     if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))


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