[PATCH] D48772: [AMDGPU] Add VALU to V_INTERP Instructions

[Ryan Taylor via Phabricator via llvm-commits]

rtaylor updated this revision to Diff 153542.
rtaylor added a comment.

Adding GCN-NEXT in test case


Repository:
  rL LLVM

https://reviews.llvm.org/D48772

Files:
  lib/Target/AMDGPU/SIInstrFormats.td
  test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir


Index: test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
@@ -0,0 +1,19 @@
+# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+
+# GCN-LABEL: name: hazard_buffer_store_v_interp
+# GCN:    bb.0.entry:
+# GCN-NEXT:    BUFFER_STORE_DWORDX4_OFFSET_exact
+# GCN-NEXT:    S_NOP
+# GCN-NEXT:    V_INTERP_P1_F32
+
+name:            hazard_buffer_store_v_interp
+body:             |
+  bb.0.entry:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
+  
+    BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec
+    $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
+    S_ENDPGM
+
+...
Index: lib/Target/AMDGPU/SIInstrFormats.td
===================================================================
--- lib/Target/AMDGPU/SIInstrFormats.td
+++ lib/Target/AMDGPU/SIInstrFormats.td
@@ -319,6 +319,7 @@
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
+  let VALU = 1;
 }
 
 class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :


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