[PATCH] D48725: [SLP] Vectorize bit-parallel operations with SWAR.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

About the division of labor:

1. I don't think instcombine can handle any of the cases shown here because it doesn't have the machinery to combine multiple independent values. So SLP or DAG are the options AFAIK.
2. Instcombine could handle something like the xor example from https://bugs.llvm.org/show_bug.cgi?id=32119 , but it's probably better suited for AggressiveInstCombine because that's not a fixed pattern (we have to increase the matcher as the width of the value grows).


Repository:
  rL LLVM

https://reviews.llvm.org/D48725