[llvm] r335924 - [InstCombine] adjust shuffle tests; NFC

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 28 14:14:02 PDT 2018


Author: spatel
Date: Thu Jun 28 14:14:02 2018
New Revision: 335924

URL: http://llvm.org/viewvc/llvm-project?rev=335924&view=rev
Log:
[InstCombine] adjust shuffle tests; NFC

Use xor for the extra uses test because div/rem have other problems.

Modified:
    llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll

Modified: llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll?rev=335924&r1=335923&r2=335924&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll Thu Jun 28 14:14:02 2018
@@ -358,17 +358,21 @@ define <4 x i32> @or_2_vars(<4 x i32> %v
   ret <4 x i32> %t3
 }
 
+; But we don't transform if both intermediate values have extra uses.
+
 define <4 x i32> @xor_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
 ; CHECK-LABEL: @xor_2_vars(
-; CHECK-NEXT:    [[T1:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 1, i32 undef, i32 3, i32 4>
+; CHECK-NEXT:    [[T1:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
 ; CHECK-NEXT:    [[T2:%.*]] = xor <4 x i32> [[V1:%.*]], <i32 5, i32 6, i32 7, i32 8>
 ; CHECK-NEXT:    [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+; CHECK-NEXT:    call void @use_v4i32(<4 x i32> [[T1]])
 ; CHECK-NEXT:    call void @use_v4i32(<4 x i32> [[T2]])
 ; CHECK-NEXT:    ret <4 x i32> [[T3]]
 ;
   %t1 = xor <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
   %t2 = xor <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
   %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+  call void @use_v4i32(<4 x i32> %t1)
   call void @use_v4i32(<4 x i32> %t2)
   ret <4 x i32> %t3
 }
@@ -380,15 +384,11 @@ define <4 x i32> @udiv_2_vars(<4 x i32>
 ; CHECK-NEXT:    [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
 ; CHECK-NEXT:    [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
-; CHECK-NEXT:    call void @use_v4i32(<4 x i32> [[T1]])
-; CHECK-NEXT:    call void @use_v4i32(<4 x i32> [[T2]])
 ; CHECK-NEXT:    ret <4 x i32> [[T3]]
 ;
   %t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
   %t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
   %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
-  call void @use_v4i32(<4 x i32> %t1)
-  call void @use_v4i32(<4 x i32> %t2)
   ret <4 x i32> %t3
 }
 




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