[llvm] r335871 - Revert "[DAGCombiner] Ensure we use the correct CC result type in visitSDIV"

[Haojian Wu via llvm-commits]

Author: hokein
Date: Thu Jun 28 09:25:57 2018
New Revision: 335871

URL: http://llvm.org/viewvc/llvm-project?rev=335871&view=rev
Log:
Revert "[DAGCombiner] Ensure we use the correct CC result type in visitSDIV"

This reverts commit r335821.

This crashes the webassembly test, run "ninja check-llvm-codegen-webassembly" to reproduce.

Removed:
    llvm/trunk/test/CodeGen/Hexagon/sdiv-minsigned.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/combine-sdiv.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=335871&r1=335870&r2=335871&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun 28 09:25:57 2018
@@ -3008,7 +3008,6 @@ SDValue DAGCombiner::visitSDIV(SDNode *N
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N->getValueType(0);
-  EVT CCVT = getSetCCResultType(VT);
   unsigned BitWidth = VT.getScalarSizeInBits();
 
   // fold vector ops
@@ -3031,7 +3030,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N
     return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
   // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
   if (N1C && N1C->getAPIntValue().isMinSignedValue())
-    return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
+    return DAG.getSelect(DL, VT, DAG.getSetCC(DL, VT, N0, N1, ISD::SETEQ),
                          DAG.getConstant(1, DL, VT),
                          DAG.getConstant(0, DL, VT));
 
@@ -3101,12 +3100,12 @@ SDValue DAGCombiner::visitSDIV(SDNode *N
     SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
 
     // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
-    SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
-    SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
+    SDValue Res = DAG.getSelect(
+        DL, VT, DAG.getSetCC(DL, VT, N1, Zero, ISD::SETLT), Sub, Sra);
     // Special case: (sdiv X, 1) -> X
     SDValue One = DAG.getConstant(1, DL, VT);
-    SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
-    Res = DAG.getSelect(DL, VT, IsOne, N0, Res);
+    Res = DAG.getSelect(DL, VT, DAG.getSetCC(DL, VT, N1, One, ISD::SETEQ), N0,
+                        Res);
     return Res;
   }
 

Removed: llvm/trunk/test/CodeGen/Hexagon/sdiv-minsigned.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/sdiv-minsigned.ll?rev=335870&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/sdiv-minsigned.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/sdiv-minsigned.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
-; REQUIRES: asserts
-
-; This checks for a bug in the DAG combiner where a SETCC was created with
-; an illegal return type. Make sure it compiles successfully.
-; CHECK: r0 = cmp.eq(r0,##-2147483648)
-
-define i32 @f0(i32 %a0) #0 {
-entry:
-   %v0 = sdiv i32 %a0, -2147483648
-   ret i32 %v0
-}
-
-attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" }

Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=335871&r1=335870&r2=335871&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Thu Jun 28 09:25:57 2018
@@ -77,25 +77,12 @@ define <4 x i32> @combine_vec_sdiv_by_mi
 ; AVX1-NEXT:    vpsrld $31, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
-; AVX2-LABEL: combine_vec_sdiv_by_minsigned:
-; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; AVX2-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpsrld $31, %xmm0, %xmm0
-; AVX2-NEXT:    retq
-;
-; AVX512F-LABEL: combine_vec_sdiv_by_minsigned:
-; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; AVX512F-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm0
-; AVX512F-NEXT:    vpsrld $31, %xmm0, %xmm0
-; AVX512F-NEXT:    retq
-;
-; AVX512BW-LABEL: combine_vec_sdiv_by_minsigned:
-; AVX512BW:       # %bb.0:
-; AVX512BW-NEXT:    vpcmpeqd {{.*}}(%rip){1to4}, %xmm0, %k1
-; AVX512BW-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
-; AVX512BW-NEXT:    retq
+; AVX2ORLATER-LABEL: combine_vec_sdiv_by_minsigned:
+; AVX2ORLATER:       # %bb.0:
+; AVX2ORLATER-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; AVX2ORLATER-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm0
+; AVX2ORLATER-NEXT:    vpsrld $31, %xmm0, %xmm0
+; AVX2ORLATER-NEXT:    retq
 ;
 ; XOP-LABEL: combine_vec_sdiv_by_minsigned:
 ; XOP:       # %bb.0: