[PATCH] D48706: [X86] Suppress load folding into and/or/xor if it will prevent matching btr/bts/btc.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:576
+      // BTC: (xor X, (shl 1, n))
+      if ((U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR)) {
+        if (U->getOperand(0).getOpcode() == ISD::SHL &&
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lebedev.ri wrote:
> Extra unneeded brackets
Oops. Leftover from before I realized that I had to handle both operand orders.


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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:594
+        if (U1.getOpcode() == ISD::ROTL &&
+            isa<ConstantSDNode>(U1.getOperand(0)) &&
+            cast<ConstantSDNode>(U1.getOperand(0))->getSExtValue() == -2)
----------------
xbolva00 wrote:
> dyn_cast maybe?
I was just trying to avoid another level of 'if'


Repository:
  rL LLVM

https://reviews.llvm.org/D48706