[PATCH] D48655: [X86][SSE] Support v16i8/v32i8 vector rotations

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: andreadb, spatel, craig.topper, efriedma.

This uses the same technique as for shifts - split the rotation into 4/2/1-bit partial rotations and select those partials based on the amount bit, making use of PBLENDVB if available. This halves the use of PBLENDVB compared to expanding to shifts, which can be a slow op.

Unfortunately I haven't found a decent way to share much of this code with the shift equivalent.


Repository:
  rL LLVM

https://reviews.llvm.org/D48655

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/vector-rotate-512.ll

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