[PATCH] D48594: [AArch64] Refactor of all code from rL334488 to fix disasm tests

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Thanks for fixing this!

Can you please make the commit message (and the description of this ticket) more descriptive by clearly stating the problem, which is something along the lines of:

"Refactor https://reviews.llvm.org/rL334488 Codegen support: there were instructions with the same encoding, and these duplicates have been removed. In addition, codegen has been improved by better matching of i16 values that these intrinsics take as arguments. For this we had to teach EXTRACT_SUBREG which uses TargetRegisterClass hook getSubClassWithSubReg that H-registers can be extracted from the FPR32 and FPR64 register classes"



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Comment at: lib/Target/AArch64/AArch64InstrInfo.td:4944
 // Having the same base pattern for fp <--> int totally freaks it out.
+// Split these patterns into a separate pattern
+
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I see what you've done here, but I am not sure this comment on itself will be very clear. I think just omitting it is clearer.


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Comment at: lib/Target/AArch64/AArch64RegisterInfo.cpp:78
+                                       unsigned Idx) const {
+  // The sub_8bit sub-register index is more constrained in 32-bit mode.
+  // It behaves just like the sub_8bit_hi index.
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What is this comment about?


https://reviews.llvm.org/D48594