[llvm] r335526 - [InstCombine] add tests for sdiv with sext bool divisor; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 25 14:36:09 PDT 2018
Author: spatel
Date: Mon Jun 25 14:36:09 2018
New Revision: 335526
URL: http://llvm.org/viewvc/llvm-project?rev=335526&view=rev
Log:
[InstCombine] add tests for sdiv with sext bool divisor; NFC
Modified:
llvm/trunk/test/Transforms/InstCombine/div.ll
Modified: llvm/trunk/test/Transforms/InstCombine/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/div.ll?rev=335526&r1=335525&r2=335526&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/div.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/div.ll Mon Jun 25 14:36:09 2018
@@ -5,67 +5,104 @@
define i32 @test1(i32 %A) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: ret i32 %A
+; CHECK-NEXT: ret i32 [[A:%.*]]
;
- %B = sdiv i32 %A, 1 ; <i32> [#uses=1]
+ %B = sdiv i32 %A, 1
ret i32 %B
}
define i32 @test2(i32 %A) {
- ; => Shift
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[B:%.*]] = lshr i32 %A, 3
+; CHECK-NEXT: [[B:%.*]] = lshr i32 [[A:%.*]], 3
; CHECK-NEXT: ret i32 [[B]]
;
- %B = udiv i32 %A, 8 ; <i32> [#uses=1]
+ %B = udiv i32 %A, 8
ret i32 %B
}
-define i32 @test4(i32 %A) {
- ; 0-A
-; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[B:%.*]] = sub i32 0, %A
+define i32 @sdiv_by_minus1(i32 %A) {
+; CHECK-LABEL: @sdiv_by_minus1(
+; CHECK-NEXT: [[B:%.*]] = sub i32 0, [[A:%.*]]
; CHECK-NEXT: ret i32 [[B]]
;
- %B = sdiv i32 %A, -1 ; <i32> [#uses=1]
+ %B = sdiv i32 %A, -1
ret i32 %B
}
+define <2 x i64> @sdiv_by_minus1_vec(<2 x i64> %x) {
+; CHECK-LABEL: @sdiv_by_minus1_vec(
+; CHECK-NEXT: [[DIV:%.*]] = sub <2 x i64> zeroinitializer, [[X:%.*]]
+; CHECK-NEXT: ret <2 x i64> [[DIV]]
+;
+ %div = sdiv <2 x i64> %x, <i64 -1, i64 -1>
+ ret <2 x i64> %div
+}
+
+define <2 x i64> @sdiv_by_minus1_vec_undef_elt(<2 x i64> %x) {
+; CHECK-LABEL: @sdiv_by_minus1_vec_undef_elt(
+; CHECK-NEXT: ret <2 x i64> undef
+;
+ %div = sdiv <2 x i64> %x, <i64 -1, i64 undef>
+ ret <2 x i64> %div
+}
+
+define i32 @sdiv_by_sext_minus1(i1 %x, i32 %y) {
+; CHECK-LABEL: @sdiv_by_sext_minus1(
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[X:%.*]] to i32
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[Y:%.*]], [[SEXT]]
+; CHECK-NEXT: ret i32 [[DIV]]
+;
+ %sext = sext i1 %x to i32
+ %div = sdiv i32 %y, %sext
+ ret i32 %div
+}
+
+define <2 x i32> @sdiv_by_sext_minus1_vec(<2 x i1> %x, <2 x i32> %y) {
+; CHECK-LABEL: @sdiv_by_sext_minus1_vec(
+; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i32> [[Y:%.*]], [[SEXT]]
+; CHECK-NEXT: ret <2 x i32> [[DIV]]
+;
+ %sext = sext <2 x i1> %x to <2 x i32>
+ %div = sdiv <2 x i32> %y, %sext
+ ret <2 x i32> %div
+}
+
define i32 @test5(i32 %A) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: ret i32 0
;
- %B = udiv i32 %A, -16 ; <i32> [#uses=1]
- %C = udiv i32 %B, -4 ; <i32> [#uses=1]
+ %B = udiv i32 %A, -16
+ %C = udiv i32 %B, -4
ret i32 %C
}
define i1 @test6(i32 %A) {
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %A, 123
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[A:%.*]], 123
; CHECK-NEXT: ret i1 [[TMP1]]
;
- %B = udiv i32 %A, 123 ; <i32> [#uses=1]
+ %B = udiv i32 %A, 123
; A < 123
- %C = icmp eq i32 %B, 0 ; <i1> [#uses=1]
+ %C = icmp eq i32 %B, 0
ret i1 %C
}
define i1 @test7(i32 %A) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[A_OFF:%.*]] = add i32 %A, -20
+; CHECK-NEXT: [[A_OFF:%.*]] = add i32 [[A:%.*]], -20
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[A_OFF]], 10
; CHECK-NEXT: ret i1 [[TMP1]]
;
- %B = udiv i32 %A, 10 ; <i32> [#uses=1]
+ %B = udiv i32 %A, 10
; A >= 20 && A < 30
- %C = icmp eq i32 %B, 2 ; <i1> [#uses=1]
+ %C = icmp eq i32 %B, 2
ret i1 %C
}
define <2 x i1> @test7vec(<2 x i32> %A) {
; CHECK-LABEL: @test7vec(
-; CHECK-NEXT: [[A_OFF:%.*]] = add <2 x i32> %A, <i32 -20, i32 -20>
+; CHECK-NEXT: [[A_OFF:%.*]] = add <2 x i32> [[A:%.*]], <i32 -20, i32 -20>
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> [[A_OFF]], <i32 10, i32 10>
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
@@ -76,18 +113,18 @@ define <2 x i1> @test7vec(<2 x i32> %A)
define i1 @test8(i8 %A) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i8 %A, -11
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i8 [[A:%.*]], -11
; CHECK-NEXT: ret i1 [[C]]
;
- %B = udiv i8 %A, 123 ; <i8> [#uses=1]
+ %B = udiv i8 %A, 123
; A >= 246
- %C = icmp eq i8 %B, 2 ; <i1> [#uses=1]
+ %C = icmp eq i8 %B, 2
ret i1 %C
}
define <2 x i1> @test8vec(<2 x i8> %A) {
; CHECK-LABEL: @test8vec(
-; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i8> %A, <i8 -11, i8 -11>
+; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i8> [[A:%.*]], <i8 -11, i8 -11>
; CHECK-NEXT: ret <2 x i1> [[C]]
;
%B = udiv <2 x i8> %A, <i8 123, i8 123>
@@ -97,18 +134,18 @@ define <2 x i1> @test8vec(<2 x i8> %A) {
define i1 @test9(i8 %A) {
; CHECK-LABEL: @test9(
-; CHECK-NEXT: [[C:%.*]] = icmp ult i8 %A, -10
+; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[A:%.*]], -10
; CHECK-NEXT: ret i1 [[C]]
;
- %B = udiv i8 %A, 123 ; <i8> [#uses=1]
+ %B = udiv i8 %A, 123
; A < 246
- %C = icmp ne i8 %B, 2 ; <i1> [#uses=1]
+ %C = icmp ne i8 %B, 2
ret i1 %C
}
define <2 x i1> @test9vec(<2 x i8> %A) {
; CHECK-LABEL: @test9vec(
-; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i8> %A, <i8 -10, i8 -10>
+; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i8> [[A:%.*]], <i8 -10, i8 -10>
; CHECK-NEXT: ret <2 x i1> [[C]]
;
%B = udiv <2 x i8> %A, <i8 123, i8 123>
@@ -118,28 +155,28 @@ define <2 x i1> @test9vec(<2 x i8> %A) {
define i32 @test10(i32 %X, i1 %C) {
; CHECK-LABEL: @test10(
-; CHECK-NEXT: [[R_V:%.*]] = select i1 %C, i32 6, i32 3
-; CHECK-NEXT: [[R:%.*]] = lshr i32 %X, [[R:%.*]].v
+; CHECK-NEXT: [[R_V:%.*]] = select i1 [[C:%.*]], i32 6, i32 3
+; CHECK-NEXT: [[R:%.*]] = lshr i32 [[X:%.*]], [[R_V]]
; CHECK-NEXT: ret i32 [[R]]
;
- %V = select i1 %C, i32 64, i32 8 ; <i32> [#uses=1]
- %R = udiv i32 %X, %V ; <i32> [#uses=1]
+ %V = select i1 %C, i32 64, i32 8
+ %R = udiv i32 %X, %V
ret i32 %R
}
define i32 @test11(i32 %X, i1 %C) {
; CHECK-LABEL: @test11(
-; CHECK-NEXT: [[B_V:%.*]] = select i1 %C, i32 10, i32 5
-; CHECK-NEXT: [[B:%.*]] = lshr i32 %X, [[B:%.*]].v
+; CHECK-NEXT: [[B_V:%.*]] = select i1 [[C:%.*]], i32 10, i32 5
+; CHECK-NEXT: [[B:%.*]] = lshr i32 [[X:%.*]], [[B_V]]
; CHECK-NEXT: ret i32 [[B]]
;
- %A = select i1 %C, i32 1024, i32 32 ; <i32> [#uses=1]
- %B = udiv i32 %X, %A ; <i32> [#uses=1]
+ %A = select i1 %C, i32 1024, i32 32
+ %B = udiv i32 %X, %A
ret i32 %B
}
; PR2328
-define i32 @test12(i32 %x) nounwind {
+define i32 @test12(i32 %x) {
; CHECK-LABEL: @test12(
; CHECK-NEXT: ret i32 1
;
@@ -147,7 +184,7 @@ define i32 @test12(i32 %x) nounwind {
ret i32 %tmp3
}
-define i32 @test13(i32 %x) nounwind {
+define i32 @test13(i32 %x) {
; CHECK-LABEL: @test13(
; CHECK-NEXT: ret i32 1
;
@@ -155,7 +192,7 @@ define i32 @test13(i32 %x) nounwind {
ret i32 %tmp3
}
-define i32 @test14(i8 %x) nounwind {
+define i32 @test14(i8 %x) {
; CHECK-LABEL: @test14(
; CHECK-NEXT: ret i32 0
;
@@ -165,10 +202,10 @@ define i32 @test14(i8 %x) nounwind {
}
; PR9814
-define i32 @test15(i32 %a, i32 %b) nounwind {
+define i32 @test15(i32 %a, i32 %b) {
; CHECK-LABEL: @test15(
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, -2
-; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], -2
+; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 [[A:%.*]], [[TMP1]]
; CHECK-NEXT: ret i32 [[DIV2]]
;
%shl = shl i32 1, %b
@@ -177,9 +214,9 @@ define i32 @test15(i32 %a, i32 %b) nounw
ret i32 %div2
}
-define <2 x i64> @test16(<2 x i64> %x) nounwind {
+define <2 x i64> @test16(<2 x i64> %x) {
; CHECK-LABEL: @test16(
-; CHECK-NEXT: [[DIV:%.*]] = udiv <2 x i64> %x, <i64 192, i64 192>
+; CHECK-NEXT: [[DIV:%.*]] = udiv <2 x i64> [[X:%.*]], <i64 192, i64 192>
; CHECK-NEXT: ret <2 x i64> [[DIV]]
;
%shr = lshr <2 x i64> %x, <i64 5, i64 5>
@@ -187,9 +224,9 @@ define <2 x i64> @test16(<2 x i64> %x) n
ret <2 x i64> %div
}
-define <2 x i64> @test17(<2 x i64> %x) nounwind {
+define <2 x i64> @test17(<2 x i64> %x) {
; CHECK-LABEL: @test17(
-; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> %x, <i64 -3, i64 -4>
+; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> [[X:%.*]], <i64 -3, i64 -4>
; CHECK-NEXT: ret <2 x i64> [[DIV]]
;
%neg = sub nsw <2 x i64> zeroinitializer, %x
@@ -197,18 +234,9 @@ define <2 x i64> @test17(<2 x i64> %x) n
ret <2 x i64> %div
}
-define <2 x i64> @test18(<2 x i64> %x) nounwind {
-; CHECK-LABEL: @test18(
-; CHECK-NEXT: [[DIV:%.*]] = sub <2 x i64> zeroinitializer, %x
-; CHECK-NEXT: ret <2 x i64> [[DIV]]
-;
- %div = sdiv <2 x i64> %x, <i64 -1, i64 -1>
- ret <2 x i64> %div
-}
-
define i32 @test19(i32 %x) {
; CHECK-LABEL: @test19(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 1
; CHECK-NEXT: [[A:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[A]]
;
@@ -228,9 +256,9 @@ define <2 x i32> @test19vec(<2 x i32> %x
define i32 @test20(i32 %x) {
; CHECK-LABEL: @test20(
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 %x, 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
-; CHECK-NEXT: [[A:%.*]] = select i1 [[TMP2]], i32 %x, i32 0
+; CHECK-NEXT: [[A:%.*]] = select i1 [[TMP2]], i32 [[X]], i32 0
; CHECK-NEXT: ret i32 [[A]]
;
%A = sdiv i32 1, %x
@@ -250,7 +278,7 @@ define <2 x i32> @test20vec(<2 x i32> %x
define i32 @test21(i32 %a) {
; CHECK-LABEL: @test21(
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 3
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A:%.*]], 3
; CHECK-NEXT: ret i32 [[DIV]]
;
%shl = shl nsw i32 %a, 2
@@ -260,7 +288,7 @@ define i32 @test21(i32 %a) {
define i32 @test22(i32 %a) {
; CHECK-LABEL: @test22(
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 4
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A:%.*]], 4
; CHECK-NEXT: ret i32 [[DIV]]
;
%mul = mul nsw i32 %a, 3
@@ -270,7 +298,7 @@ define i32 @test22(i32 %a) {
define i32 @test23(i32 %a) {
; CHECK-LABEL: @test23(
-; CHECK-NEXT: [[DIV:%.*]] = udiv i32 %a, 3
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], 3
; CHECK-NEXT: ret i32 [[DIV]]
;
%shl = shl nuw i32 %a, 2
@@ -280,7 +308,7 @@ define i32 @test23(i32 %a) {
define i32 @test24(i32 %a) {
; CHECK-LABEL: @test24(
-; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, 2
+; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[A:%.*]], 2
; CHECK-NEXT: ret i32 [[DIV]]
;
%mul = mul nuw i32 %a, 3
@@ -290,7 +318,7 @@ define i32 @test24(i32 %a) {
define i32 @test25(i32 %a) {
; CHECK-LABEL: @test25(
-; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 1
+; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 [[A:%.*]], 1
; CHECK-NEXT: ret i32 [[DIV]]
;
%shl = shl nsw i32 %a, 2
@@ -300,7 +328,7 @@ define i32 @test25(i32 %a) {
define i32 @test26(i32 %a) {
; CHECK-LABEL: @test26(
-; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 2
+; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 [[A:%.*]], 2
; CHECK-NEXT: ret i32 [[DIV]]
;
%mul = mul nsw i32 %a, 12
@@ -310,7 +338,7 @@ define i32 @test26(i32 %a) {
define i32 @test27(i32 %a) {
; CHECK-LABEL: @test27(
-; CHECK-NEXT: [[DIV:%.*]] = shl nuw i32 %a, 1
+; CHECK-NEXT: [[DIV:%.*]] = shl nuw i32 [[A:%.*]], 1
; CHECK-NEXT: ret i32 [[DIV]]
;
%shl = shl nuw i32 %a, 2
@@ -320,7 +348,7 @@ define i32 @test27(i32 %a) {
define i32 @test28(i32 %a) {
; CHECK-LABEL: @test28(
-; CHECK-NEXT: [[DIV:%.*]] = mul nuw i32 %a, 12
+; CHECK-NEXT: [[DIV:%.*]] = mul nuw i32 [[A:%.*]], 12
; CHECK-NEXT: ret i32 [[DIV]]
;
%mul = mul nuw i32 %a, 36
@@ -330,7 +358,7 @@ define i32 @test28(i32 %a) {
define i32 @test29(i32 %a) {
; CHECK-LABEL: @test29(
-; CHECK-NEXT: [[MUL_LOBIT:%.*]] = and i32 %a, 1
+; CHECK-NEXT: [[MUL_LOBIT:%.*]] = and i32 [[A:%.*]], 1
; CHECK-NEXT: ret i32 [[MUL_LOBIT]]
;
%mul = shl nsw i32 %a, 31
@@ -340,7 +368,7 @@ define i32 @test29(i32 %a) {
define i32 @test30(i32 %a) {
; CHECK-LABEL: @test30(
-; CHECK-NEXT: ret i32 %a
+; CHECK-NEXT: ret i32 [[A:%.*]]
;
%mul = shl nuw i32 %a, 31
%div = udiv i32 %mul, -2147483648
@@ -358,9 +386,9 @@ define <2 x i32> @test31(<2 x i32> %x) {
define i32 @test32(i32 %a, i32 %b) {
; CHECK-LABEL: @test32(
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, %b
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, [[B:%.*]]
; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[SHL]], 2
-; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
+; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 [[A:%.*]], [[DIV]]
; CHECK-NEXT: ret i32 [[DIV2]]
;
%shl = shl i32 2, %b
@@ -369,9 +397,9 @@ define i32 @test32(i32 %a, i32 %b) {
ret i32 %div2
}
-define <2 x i64> @test33(<2 x i64> %x) nounwind {
+define <2 x i64> @test33(<2 x i64> %x) {
; CHECK-LABEL: @test33(
-; CHECK-NEXT: [[DIV:%.*]] = udiv exact <2 x i64> %x, <i64 192, i64 192>
+; CHECK-NEXT: [[DIV:%.*]] = udiv exact <2 x i64> [[X:%.*]], <i64 192, i64 192>
; CHECK-NEXT: ret <2 x i64> [[DIV]]
;
%shr = lshr exact <2 x i64> %x, <i64 5, i64 5>
@@ -379,9 +407,9 @@ define <2 x i64> @test33(<2 x i64> %x) n
ret <2 x i64> %div
}
-define <2 x i64> @test34(<2 x i64> %x) nounwind {
+define <2 x i64> @test34(<2 x i64> %x) {
; CHECK-LABEL: @test34(
-; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i64> %x, <i64 -3, i64 -4>
+; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i64> [[X:%.*]], <i64 -3, i64 -4>
; CHECK-NEXT: ret <2 x i64> [[DIV]]
;
%neg = sub nsw <2 x i64> zeroinitializer, %x
@@ -391,7 +419,7 @@ define <2 x i64> @test34(<2 x i64> %x) n
define i32 @test35(i32 %A) {
; CHECK-LABEL: @test35(
-; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 2147483647
; CHECK-NEXT: [[MUL:%.*]] = udiv exact i32 [[AND]], 2147483647
; CHECK-NEXT: ret i32 [[MUL]]
;
@@ -413,8 +441,8 @@ define <2 x i32> @test35vec(<2 x i32> %A
define i32 @test36(i32 %A) {
; CHECK-LABEL: @test36(
-; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647
-; CHECK-NEXT: [[MUL:%.*]] = lshr exact i32 [[AND]], %A
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 2147483647
+; CHECK-NEXT: [[MUL:%.*]] = lshr exact i32 [[AND]], [[A]]
; CHECK-NEXT: ret i32 [[MUL]]
;
%and = and i32 %A, 2147483647
@@ -438,10 +466,10 @@ define <2 x i32> @test36vec(<2 x i32> %A
define i32 @test37(i32* %b) {
; CHECK-LABEL: @test37(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store i32 0, i32* %b, align 4
-; CHECK-NEXT: br i1 undef, label %lor.rhs, label %lor.end
+; CHECK-NEXT: store i32 0, i32* [[B:%.*]], align 4
+; CHECK-NEXT: br i1 undef, label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
; CHECK: lor.rhs:
-; CHECK-NEXT: br label %lor.end
+; CHECK-NEXT: br label [[LOR_END]]
; CHECK: lor.end:
; CHECK-NEXT: ret i32 0
;
@@ -464,7 +492,7 @@ lor.end:
define i32 @shrink(i8 %x) {
; CHECK-LABEL: @shrink(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv i8 %x, 127
+; CHECK-NEXT: [[TMP1:%.*]] = sdiv i8 [[X:%.*]], 127
; CHECK-NEXT: [[DIV:%.*]] = sext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[DIV]]
;
@@ -477,7 +505,7 @@ define i32 @shrink(i8 %x) {
define i32 @zap(i8 %x) {
; CHECK-LABEL: @zap(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %x, -128
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], -128
; CHECK-NEXT: [[DIV:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[DIV]]
;
@@ -490,7 +518,7 @@ define i32 @zap(i8 %x) {
define <3 x i32> @shrink_vec(<3 x i8> %x) {
; CHECK-LABEL: @shrink_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv <3 x i8> %x, <i8 127, i8 127, i8 127>
+; CHECK-NEXT: [[TMP1:%.*]] = sdiv <3 x i8> [[X:%.*]], <i8 127, i8 127, i8 127>
; CHECK-NEXT: [[DIV:%.*]] = sext <3 x i8> [[TMP1]] to <3 x i32>
; CHECK-NEXT: ret <3 x i32> [[DIV]]
;
@@ -501,7 +529,7 @@ define <3 x i32> @shrink_vec(<3 x i8> %x
define <2 x i32> @zap_vec(<2 x i8> %x) {
; CHECK-LABEL: @zap_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, <i8 -128, i8 -128>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -128, i8 -128>
; CHECK-NEXT: [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[DIV]]
;
@@ -514,7 +542,7 @@ define <2 x i32> @zap_vec(<2 x i8> %x) {
define i32 @shrink_no(i8 %x) {
; CHECK-LABEL: @shrink_no(
-; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32
+; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 128
; CHECK-NEXT: ret i32 [[DIV]]
;
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