[llvm] r334980 - [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.
Vlad Tsyrklevich via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 25 10:43:47 PDT 2018
I took a look at this again since we're still seeing occasional build
timeouts on the UBSan bot. I recorded the # of basic blocks on entry to the
jump threading pass for printAliasInstr() with different build settings:
-O1: ~5.5k BBs
-O2: ~25k BBs
-O3: ~25k BBs
-O3 + sanitizers: ~54k BBs
The blow-up between -O1 and -O2 is due to the inliner inlining
MCInst::getOperand() and MCRegisterInfo::getRegClass() many times. By
adding a CFGSimplificationPass before the JumpThreadingPass runs, the
number of BBs is brought down to:
-O2 : ~15k BBs
-O3 -fsanitize: ~42k BBs
This corresponds with ~30s/2m local build runtimes, approximately a ~4x
improvement. Not sure if this change is worth pursuing given that it may
only benefit compile times for huge functions.
On Tue, Jun 19, 2018 at 5:09 PM Vlad Tsyrklevich <vlad at tsyrklevich.net>
wrote:
> Hi Sander, this change has started causing intermittent build timeouts on
> the ubsan builder:
> http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan
>
> I've tracked it down to this change, before this
> change AArch64InstPrinter.cpp takes ~95s to build with -O3 locally, with
> this change it takes 120s. With sanitizers enabled, this increase is
> multiplied by 5-15x, and the builder in the cloud is even slower. Taking a
> brief look at what's happening in the compiler, it looks like most of the
> time is spent recomputing dominator trees in the JumpThreading pass
> for llvm::AArch64AppleInstPrinter::printAliasInstr(). Looking at the IR for
> printAliasInstr(), it contains a switch statement with many targets and
> every statement in the switch is inlining multiple functions
> (like MCInst::getOperand and MCRegisterInfo::getRegClass) multiple
> times significantly multiplying the number of basic blocks in the function.
>
> I've reverted this change and r334983 for now in r335085.
>
> On Mon, Jun 18, 2018 at 1:54 PM Sander de Smalen via llvm-commits <
> llvm-commits at lists.llvm.org> wrote:
>
>> Author: s.desmalen
>> Date: Mon Jun 18 13:50:33 2018
>> New Revision: 334980
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=334980&view=rev
>> Log:
>> [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar)
>> instructions.
>>
>> The variants added by this patch are:
>> - SQINC signed increment, e.g. sqinc x0, w0, all, mul #4
>> - SQDEC signed decrement, e.g. sqdec x0, w0, all, mul #4
>> - UQINC unsigned increment, e.g. uqinc w0, all, mul #4
>> - UQDEC unsigned decrement, e.g. uqdec w0, all, mul #4
>>
>> This patch includes asmparser changes to parse a GPR64 as a GPR32 in
>> order to satisfy the constraint check:
>> x0 == GPR64(w0)
>> in:
>> sqinc x0, w0, all, mul #4
>> ^___^ (must match)
>>
>> Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
>>
>> Reviewed By: fhahn
>>
>> Differential Revision: https://reviews.llvm.org/D47716
>>
>>
>> Modified:
>> llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
>> llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
>> llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
>> llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
>> llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
>> llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
>> llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdecb.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdecd.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdech.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqdecw.s
>> llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqincb.s
>> llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqincd.s
>> llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqinch.s
>> llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/sqincw.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdecb.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdecd.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdech.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqdecw.s
>> llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqincb.s
>> llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqincd.s
>> llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqinch.s
>> llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s
>> llvm/trunk/test/MC/AArch64/SVE/uqincw.s
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Mon Jun 18
>> 13:50:33 2018
>> @@ -179,11 +179,23 @@ def CondCode : AsmOperandClass {
>> // A 32-bit register pasrsed as 64-bit
>> def GPR32as64Operand : AsmOperandClass {
>> let Name = "GPR32as64";
>> + let ParserMethod =
>> + "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSubReg>";
>> }
>> def GPR32as64 : RegisterOperand<GPR32> {
>> let ParserMatchClass = GPR32as64Operand;
>> }
>>
>> +// A 64-bit register pasrsed as 32-bit
>> +def GPR64as32Operand : AsmOperandClass {
>> + let Name = "GPR64as32";
>> + let ParserMethod =
>> + "tryParseGPROperand<false,
>> RegConstraintEqualityTy::EqualsSuperReg>";
>> +}
>> +def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> {
>> + let ParserMatchClass = GPR64as32Operand;
>> +}
>> +
>> // 8-bit immediate for AdvSIMD where 64-bit values of the form:
>> // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg
>> hhhhhhhh
>> // are encoded as the eight bit value 'abcdefgh'.
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Jun 18
>> 13:50:33 2018
>> @@ -527,21 +527,37 @@ let Predicates = [HasSVE] in {
>> defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
>> defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
>>
>> + defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">;
>> + defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">;
>> + defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">;
>> + defm UQDECB_WPiI : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">;
>> defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
>> defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
>> defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
>> defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
>>
>> + defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">;
>> + defm UQINCH_WPiI : sve_int_pred_pattern_b_u32<0b01001, "uqinch">;
>> + defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">;
>> + defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech">;
>> defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
>> defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
>> defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
>> defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
>>
>> + defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">;
>> + defm UQINCW_WPiI : sve_int_pred_pattern_b_u32<0b10001, "uqincw">;
>> + defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">;
>> + defm UQDECW_WPiI : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">;
>> defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
>> defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
>> defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
>> defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
>>
>> + defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">;
>> + defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd">;
>> + defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">;
>> + defm UQDECD_WPiI : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">;
>> defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
>> defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
>> defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Mon Jun
>> 18 13:50:33 2018
>> @@ -66,6 +66,12 @@ enum class RegKind {
>> SVEPredicateVector
>> };
>>
>> +enum RegConstraintEqualityTy {
>> + EqualsReg,
>> + EqualsSuperReg,
>> + EqualsSubReg
>> +};
>> +
>> class AArch64AsmParser : public MCTargetAsmParser {
>> private:
>> StringRef Mnemonic; ///< Instruction mnemonic.
>> @@ -92,7 +98,8 @@ private:
>> bool parseOperand(OperandVector &Operands, bool isCondCode,
>> bool invertCondCode);
>>
>> - bool showMatchError(SMLoc Loc, unsigned ErrCode, OperandVector
>> &Operands);
>> + bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,
>> + OperandVector &Operands);
>>
>> bool parseDirectiveArch(SMLoc L);
>> bool parseDirectiveCPU(SMLoc L);
>> @@ -139,7 +146,8 @@ private:
>> bool tryParseNeonVectorRegister(OperandVector &Operands);
>> OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
>> OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
>> - template <bool ParseShiftExtend>
>> + template <bool ParseShiftExtend,
>> + RegConstraintEqualityTy EqTy =
>> RegConstraintEqualityTy::EqualsReg>
>> OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
>> template <bool ParseShiftExtend, bool ParseSuffix>
>> OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
>> @@ -177,6 +185,8 @@ public:
>>
>> setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
>> }
>>
>> + bool regsEqual(const MCParsedAsmOperand &Op1,
>> + const MCParsedAsmOperand &Op2) const override;
>> bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
>> SMLoc NameLoc, OperandVector &Operands) override;
>> bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
>> override;
>> @@ -231,6 +241,10 @@ private:
>> RegKind Kind;
>> int ElementWidth;
>>
>> + // The register may be allowed as a different register class,
>> + // e.g. for GPR64as32 or GPR32as64.
>> + RegConstraintEqualityTy EqualityTy;
>> +
>> // In some cases the shift/extend needs to be explicitly parsed
>> together
>> // with the register, rather than as a separate operand. This is
>> needed
>> // for addressing modes where the instruction as a whole dictates the
>> @@ -446,6 +460,11 @@ public:
>> return Reg.RegNum;
>> }
>>
>> + RegConstraintEqualityTy getRegEqualityTy() const {
>> + assert(Kind == k_Register && "Invalid access!");
>> + return Reg.EqualityTy;
>> + }
>> +
>> unsigned getVectorListStart() const {
>> assert(Kind == k_VectorList && "Invalid access!");
>> return VectorList.RegNum;
>> @@ -1002,6 +1021,11 @@ public:
>>
>> AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
>> }
>>
>> + bool isGPR64as32() const {
>> + return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
>> +
>> AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
>> + }
>> +
>> bool isWSeqPair() const {
>> return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
>>
>> AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
>> @@ -1318,6 +1342,18 @@ public:
>> Inst.addOperand(MCOperand::createReg(Reg));
>> }
>>
>> + void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
>> + assert(N == 1 && "Invalid number of operands!");
>> + assert(
>> +
>> AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
>> +
>> + const MCRegisterInfo *RI = Ctx.getRegisterInfo();
>> + uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
>> + RI->getEncodingValue(getReg()));
>> +
>> + Inst.addOperand(MCOperand::createReg(Reg));
>> + }
>> +
>> template <int Width>
>> void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
>> unsigned Base;
>> @@ -1668,6 +1704,7 @@ public:
>>
>> static std::unique_ptr<AArch64Operand>
>> CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext
>> &Ctx,
>> + RegConstraintEqualityTy EqTy =
>> RegConstraintEqualityTy::EqualsReg,
>> AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
>> unsigned ShiftAmount = 0,
>> unsigned HasExplicitAmount = false) {
>> @@ -1675,6 +1712,7 @@ public:
>> Op->Reg.RegNum = RegNum;
>> Op->Reg.Kind = Kind;
>> Op->Reg.ElementWidth = 0;
>> + Op->Reg.EqualityTy = EqTy;
>> Op->Reg.ShiftExtend.Type = ExtTy;
>> Op->Reg.ShiftExtend.Amount = ShiftAmount;
>> Op->Reg.ShiftExtend.HasExplicitAmount = HasExplicitAmount;
>> @@ -1692,7 +1730,7 @@ public:
>> assert((Kind == RegKind::NeonVector || Kind ==
>> RegKind::SVEDataVector ||
>> Kind == RegKind::SVEPredicateVector) &&
>> "Invalid vector kind");
>> - auto Op = CreateReg(RegNum, Kind, S, E, Ctx, ExtTy, ShiftAmount,
>> + auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy,
>> ShiftAmount,
>> HasExplicitAmount);
>> Op->Reg.ElementWidth = ElementWidth;
>> return Op;
>> @@ -3164,7 +3202,7 @@ AArch64AsmParser::tryParseGPR64sp0Operan
>> return MatchOperand_Success;
>> }
>>
>> -template <bool ParseShiftExtend>
>> +template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy>
>> OperandMatchResultTy
>> AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
>> SMLoc StartLoc = getLoc();
>> @@ -3177,7 +3215,7 @@ AArch64AsmParser::tryParseGPROperand(Ope
>> // No shift/extend is the default.
>> if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) {
>> Operands.push_back(AArch64Operand::CreateReg(
>> - RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
>> + RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(),
>> EqTy));
>> return MatchOperand_Success;
>> }
>>
>> @@ -3191,10 +3229,10 @@ AArch64AsmParser::tryParseGPROperand(Ope
>> return Res;
>>
>> auto Ext = static_cast<AArch64Operand*>(ExtOpnd.back().get());
>> - Operands.push_back(AArch64Operand::CreateReg(RegNum, RegKind::Scalar,
>> - StartLoc, Ext->getEndLoc(), getContext(),
>> - Ext->getShiftExtendType(),
>> Ext->getShiftExtendAmount(),
>> - Ext->hasShiftExtendAmount()));
>> + Operands.push_back(AArch64Operand::CreateReg(
>> + RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(),
>> EqTy,
>> + Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
>> + Ext->hasShiftExtendAmount()));
>>
>> return MatchOperand_Success;
>> }
>> @@ -3412,6 +3450,30 @@ bool AArch64AsmParser::parseOperand(Oper
>> }
>> }
>>
>> +bool AArch64AsmParser::regsEqual(const MCParsedAsmOperand &Op1,
>> + const MCParsedAsmOperand &Op2) const {
>> + auto &AOp1 = static_cast<const AArch64Operand&>(Op1);
>> + auto &AOp2 = static_cast<const AArch64Operand&>(Op2);
>> + if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg &&
>> + AOp2.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg)
>> + return MCTargetAsmParser::regsEqual(Op1, Op2);
>> +
>> + assert(AOp1.isScalarReg() && AOp2.isScalarReg() &&
>> + "Testing equality of non-scalar registers not supported");
>> +
>> + // Check if a registers match their sub/super register classes.
>> + if (AOp1.getRegEqualityTy() == EqualsSuperReg)
>> + return getXRegFromWReg(Op1.getReg()) == Op2.getReg();
>> + if (AOp1.getRegEqualityTy() == EqualsSubReg)
>> + return getWRegFromXReg(Op1.getReg()) == Op2.getReg();
>> + if (AOp2.getRegEqualityTy() == EqualsSuperReg)
>> + return getXRegFromWReg(Op2.getReg()) == Op1.getReg();
>> + if (AOp2.getRegEqualityTy() == EqualsSubReg)
>> + return getWRegFromXReg(Op2.getReg()) == Op1.getReg();
>> +
>> + return false;
>> +}
>> +
>> /// ParseInstruction - Parse an AArch64 instruction mnemonic followed by
>> its
>> /// operands.
>> bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
>> @@ -3765,10 +3827,22 @@ static std::string AArch64MnemonicSpellC
>> unsigned VariantID = 0);
>>
>> bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
>> + uint64_t ErrorInfo,
>> OperandVector &Operands) {
>> switch (ErrCode) {
>> - case Match_InvalidTiedOperand:
>> - return Error(Loc, "operand must match destination register");
>> + case Match_InvalidTiedOperand: {
>> + RegConstraintEqualityTy EqTy =
>> + static_cast<const AArch64Operand &>(*Operands[ErrorInfo])
>> + .getRegEqualityTy();
>> + switch (EqTy) {
>> + case RegConstraintEqualityTy::EqualsSubReg:
>> + return Error(Loc, "operand must be 64-bit form of destination
>> register");
>> + case RegConstraintEqualityTy::EqualsSuperReg:
>> + return Error(Loc, "operand must be 32-bit form of destination
>> register");
>> + case RegConstraintEqualityTy::EqualsReg:
>> + return Error(Loc, "operand must match destination register");
>> + }
>> + }
>> case Match_MissingFeature:
>> return Error(Loc,
>> "instruction requires a CPU feature not currently
>> enabled");
>> @@ -4389,7 +4463,7 @@ bool AArch64AsmParser::MatchAndEmitInstr
>> return Error(IDLoc, Msg);
>> }
>> case Match_MnemonicFail:
>> - return showMatchError(IDLoc, MatchResult, Operands);
>> + return showMatchError(IDLoc, MatchResult, ErrorInfo, Operands);
>> case Match_InvalidOperand: {
>> SMLoc ErrorLoc = IDLoc;
>>
>> @@ -4408,7 +4482,7 @@ bool AArch64AsmParser::MatchAndEmitInstr
>> ((AArch64Operand &)*Operands[ErrorInfo]).isTokenSuffix())
>> MatchResult = Match_InvalidSuffix;
>>
>> - return showMatchError(ErrorLoc, MatchResult, Operands);
>> + return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);
>> }
>> case Match_InvalidTiedOperand:
>> case Match_InvalidMemoryIndexed1:
>> @@ -4546,7 +4620,7 @@ bool AArch64AsmParser::MatchAndEmitInstr
>> SMLoc ErrorLoc = ((AArch64Operand
>> &)*Operands[ErrorInfo]).getStartLoc();
>> if (ErrorLoc == SMLoc())
>> ErrorLoc = IDLoc;
>> - return showMatchError(ErrorLoc, MatchResult, Operands);
>> + return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);
>> }
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp Mon
>> Jun 18 13:50:33 2018
>> @@ -1527,3 +1527,10 @@ void AArch64InstPrinter::printExactFPImm
>> unsigned Val = MI->getOperand(OpNum).getImm();
>> O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
>> }
>> +
>> +void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
>> + const MCSubtargetInfo &STI,
>> + raw_ostream &O) {
>> + unsigned Reg = MI->getOperand(OpNum).getReg();
>> + O << getRegisterName(getWRegFromXReg(Reg));
>> +}
>>
>> Modified: llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h Mon
>> Jun 18 13:50:33 2018
>> @@ -180,6 +180,8 @@ protected:
>> template <char = 0>
>> void printSVERegOp(const MCInst *MI, unsigned OpNum,
>> const MCSubtargetInfo &STI, raw_ostream &O);
>> + void printGPR64as32(const MCInst *MI, unsigned OpNum,
>> + const MCSubtargetInfo &STI, raw_ostream &O);
>> template <int Width>
>> void printZPRasFPR(const MCInst *MI, unsigned OpNum,
>> const MCSubtargetInfo &STI, raw_ostream &O);
>>
>> Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Jun 18 13:50:33
>> 2018
>> @@ -333,9 +333,32 @@ class sve_int_pred_pattern_b<bits<5> opc
>> let Inst{9-5} = pattern;
>> let Inst{4-0} = Rdn;
>>
>> + // Signed 32bit forms require their GPR operand printed.
>> + let AsmString = !if(!eq(opc{2,0}, 0b00),
>> + !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul
>> $imm4"),
>> + !strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));
>> +
>> let Constraints = "$Rdn = $_Rdn";
>> }
>>
>> +multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> {
>> + def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;
>> +
>> + def : InstAlias<asm # "\t$Rd, $Rn, $pattern",
>> + (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn,
>> sve_pred_enum:$pattern, 1), 1>;
>> + def : InstAlias<asm # "\t$Rd, $Rn",
>> + (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn,
>> 0b11111, 1), 2>;
>> +}
>> +
>> +multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> {
>> + def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;
>> +
>> + def : InstAlias<asm # "\t$Rdn, $pattern",
>> + (!cast<Instruction>(NAME) GPR32z:$Rdn,
>> sve_pred_enum:$pattern, 1), 1>;
>> + def : InstAlias<asm # "\t$Rdn",
>> + (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;
>> +}
>> +
>> multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
>> def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqdecb sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqdecb x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqdecb x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqdecb x0, x1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqdecb x0, x1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqdecb x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecb.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdecb.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdecb.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqdecb x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqdecb x0, w0
>> +// CHECK-INST: sqdecb x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
>> +
>> +sqdecb x0, w0, all
>> +// CHECK-INST: sqdecb x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
>> +
>> +sqdecb x0, w0, all, mul #1
>> +// CHECK-INST: sqdecb x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
>> +
>> +sqdecb x0, w0, all, mul #16
>> +// CHECK-INST: sqdecb x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 2f 04 <unknown>
>> +
>> +sqdecb x0, w0, pow2
>> +// CHECK-INST: sqdecb x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf8,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 20 04 <unknown>
>> +
>> +sqdecb x0, w0, pow2, mul #16
>> +// CHECK-INST: sqdecb x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf8,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 2f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqdecd sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqdecd x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqdecd x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqdecd x0, x1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqdecd x0, x1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqdecd x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecd.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdecd.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdecd.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqdecd x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqdecd x0, w0
>> +// CHECK-INST: sqdecd x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
>> +
>> +sqdecd x0, w0, all
>> +// CHECK-INST: sqdecd x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
>> +
>> +sqdecd x0, w0, all, mul #1
>> +// CHECK-INST: sqdecd x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
>> +
>> +sqdecd x0, w0, all, mul #16
>> +// CHECK-INST: sqdecd x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xfb,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb ef 04 <unknown>
>> +
>> +sqdecd x0, w0, pow2
>> +// CHECK-INST: sqdecd x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf8,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 e0 04 <unknown>
>> +
>> +sqdecd x0, w0, pow2, mul #16
>> +// CHECK-INST: sqdecd x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf8,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqdech sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqdech x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqdech x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqdech x0, x1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqdech x0, x1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqdech x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdech.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdech.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdech.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqdech x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqdech x0, w0
>> +// CHECK-INST: sqdech x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
>> +
>> +sqdech x0, w0, all
>> +// CHECK-INST: sqdech x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
>> +
>> +sqdech x0, w0, all, mul #1
>> +// CHECK-INST: sqdech x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
>> +
>> +sqdech x0, w0, all, mul #16
>> +// CHECK-INST: sqdech x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb 6f 04 <unknown>
>> +
>> +sqdech x0, w0, pow2
>> +// CHECK-INST: sqdech x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf8,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 60 04 <unknown>
>> +
>> +sqdech x0, w0, pow2, mul #16
>> +// CHECK-INST: sqdech x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf8,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 6f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqdecw sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqdecw x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqdecw x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqdecw x0, x1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqdecw x0, x1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqdecw x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecw.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqdecw.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqdecw.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqdecw x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqdecw x0, w0
>> +// CHECK-INST: sqdecw x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
>> +
>> +sqdecw x0, w0, all
>> +// CHECK-INST: sqdecw x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
>> +
>> +sqdecw x0, w0, all, mul #1
>> +// CHECK-INST: sqdecw x0, w0
>> +// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
>> +
>> +sqdecw x0, w0, all, mul #16
>> +// CHECK-INST: sqdecw x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 fb af 04 <unknown>
>> +
>> +sqdecw x0, w0, pow2
>> +// CHECK-INST: sqdecw x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf8,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 a0 04 <unknown>
>> +
>> +sqdecw x0, w0, pow2, mul #16
>> +// CHECK-INST: sqdecw x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf8,0xaf,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f8 af 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqincb sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqincb x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqincb x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqincb x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqincb x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqincb x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqincb.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqincb.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqincb.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqincb x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqincb x0, w0
>> +// CHECK-INST: sqincb x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
>> +
>> +sqincb x0, w0, all
>> +// CHECK-INST: sqincb x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
>> +
>> +sqincb x0, w0, all, mul #1
>> +// CHECK-INST: sqincb x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
>> +
>> +sqincb x0, w0, all, mul #16
>> +// CHECK-INST: sqincb x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 2f 04 <unknown>
>> +
>> +sqincb x0, w0, pow2
>> +// CHECK-INST: sqincb x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf0,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 20 04 <unknown>
>> +
>> +sqincb x0, w0, pow2, mul #16
>> +// CHECK-INST: sqincb x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf0,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 2f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqincd sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqincd x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqincd x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqincd x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqincd x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqincd x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqincd.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqincd.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqincd.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqincd x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqincd x0, w0
>> +// CHECK-INST: sqincd x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
>> +
>> +sqincd x0, w0, all
>> +// CHECK-INST: sqincd x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
>> +
>> +sqincd x0, w0, all, mul #1
>> +// CHECK-INST: sqincd x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
>> +
>> +sqincd x0, w0, all, mul #16
>> +// CHECK-INST: sqincd x0, w0, all
>> +// CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 ef 04 <unknown>
>> +
>> +sqincd x0, w0, pow2
>> +// CHECK-INST: sqincd x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 e0 04 <unknown>
>> +
>> +sqincd x0, w0, pow2, mul #16
>> +// CHECK-INST: sqincd x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf0,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 ef 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqinch sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqinch x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqinch x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqinch x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqinch x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqinch x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqinch.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqinch.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqinch.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqinch x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqinch x0, w0
>> +// CHECK-INST: sqinch x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
>> +
>> +sqinch x0, w0, all
>> +// CHECK-INST: sqinch x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
>> +
>> +sqinch x0, w0, all, mul #1
>> +// CHECK-INST: sqinch x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
>> +
>> +sqinch x0, w0, all, mul #16
>> +// CHECK-INST: sqinch x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 6f 04 <unknown>
>> +
>> +sqinch x0, w0, pow2
>> +// CHECK-INST: sqinch x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf0,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 60 04 <unknown>
>> +
>> +sqinch x0, w0, pow2, mul #16
>> +// CHECK-INST: sqinch x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf0,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 6f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -20,6 +20,20 @@ sqincw sp
>>
>>
>> //
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up
>> +
>> +sqincw x0, w1
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of
>> destination register
>> +// CHECK-NEXT: sqincw x0, w1
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +sqincw x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: sqincw x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> +//
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>> sqincw x0, all, mul #-1
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/sqincw.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/sqincw.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/sqincw.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ sqincw x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (x0, w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +sqincw x0, w0
>> +// CHECK-INST: sqincw x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
>> +
>> +sqincw x0, w0, all
>> +// CHECK-INST: sqincw x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
>> +
>> +sqincw x0, w0, all, mul #1
>> +// CHECK-INST: sqincw x0, w0
>> +// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
>> +
>> +sqincw x0, w0, all, mul #16
>> +// CHECK-INST: sqincw x0, w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f3 af 04 <unknown>
>> +
>> +sqincw x0, w0, pow2
>> +// CHECK-INST: sqincw x0, w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 a0 04 <unknown>
>> +
>> +sqincw x0, w0, pow2, mul #16
>> +// CHECK-INST: sqincw x0, w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f0 af 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqdecb w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqdecb w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqdecb wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqdecb wsp
>> @@ -19,6 +14,25 @@ uqdecb sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned dec only has one register operand)
>> +
>> +uqdecb x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecb x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdecb w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecb w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdecb x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecb x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecb.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdecb.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdecb.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqdecb x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqdecb w0
>> +// CHECK-INST: uqdecb w0
>> +// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
>> +
>> +uqdecb w0, all
>> +// CHECK-INST: uqdecb w0
>> +// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
>> +
>> +uqdecb w0, all, mul #1
>> +// CHECK-INST: uqdecb w0
>> +// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
>> +
>> +uqdecb w0, all, mul #16
>> +// CHECK-INST: uqdecb w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xff,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 2f 04 <unknown>
>> +
>> +uqdecb w0, pow2
>> +// CHECK-INST: uqdecb w0, pow2
>> +// CHECK-ENCODING: [0x00,0xfc,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc 20 04 <unknown>
>> +
>> +uqdecb w0, pow2, mul #16
>> +// CHECK-INST: uqdecb w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xfc,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc 2f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqdecd w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqdecd w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqdecd wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqdecd wsp
>> @@ -19,6 +14,25 @@ uqdecd sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned dec only has one register operand)
>> +
>> +uqdecd x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecd x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdecd w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecd w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdecd x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecd x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecd.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdecd.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdecd.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqdecd x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqdecd w0
>> +// CHECK-INST: uqdecd w0
>> +// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
>> +
>> +uqdecd w0, all
>> +// CHECK-INST: uqdecd w0
>> +// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
>> +
>> +uqdecd w0, all, mul #1
>> +// CHECK-INST: uqdecd w0
>> +// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
>> +
>> +uqdecd w0, all, mul #16
>> +// CHECK-INST: uqdecd w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff ef 04 <unknown>
>> +
>> +uqdecd w0, pow2
>> +// CHECK-INST: uqdecd w0, pow2
>> +// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc e0 04 <unknown>
>> +
>> +uqdecd w0, pow2, mul #16
>> +// CHECK-INST: uqdecd w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc ef 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqdech w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqdech w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqdech wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqdech wsp
>> @@ -19,6 +14,25 @@ uqdech sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned dec only has one register operand)
>> +
>> +uqdech x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdech x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdech w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdech w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdech x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdech x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdech.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdech.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdech.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqdech x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqdech w0
>> +// CHECK-INST: uqdech w0
>> +// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
>> +
>> +uqdech w0, all
>> +// CHECK-INST: uqdech w0
>> +// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
>> +
>> +uqdech w0, all, mul #1
>> +// CHECK-INST: uqdech w0
>> +// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
>> +
>> +uqdech w0, all, mul #16
>> +// CHECK-INST: uqdech w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff 6f 04 <unknown>
>> +
>> +uqdech w0, pow2
>> +// CHECK-INST: uqdech w0, pow2
>> +// CHECK-ENCODING: [0x00,0xfc,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc 60 04 <unknown>
>> +
>> +uqdech w0, pow2, mul #16
>> +// CHECK-INST: uqdech w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc 6f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqdecw w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqdecw w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqdecw wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqdecw wsp
>> @@ -19,6 +14,25 @@ uqdecw sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned dec only has one register operand)
>> +
>> +uqdecw x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecw x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdecw w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecw w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqdecw x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqdecw x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecw.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqdecw.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqdecw.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqdecw x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqdecw w0
>> +// CHECK-INST: uqdecw w0
>> +// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
>> +
>> +uqdecw w0, all
>> +// CHECK-INST: uqdecw w0
>> +// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
>> +
>> +uqdecw w0, all, mul #1
>> +// CHECK-INST: uqdecw w0
>> +// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
>> +
>> +uqdecw w0, all, mul #16
>> +// CHECK-INST: uqdecw w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xff,0xaf,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 ff af 04 <unknown>
>> +
>> +uqdecw w0, pow2
>> +// CHECK-INST: uqdecw w0, pow2
>> +// CHECK-ENCODING: [0x00,0xfc,0xa0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc a0 04 <unknown>
>> +
>> +uqdecw w0, pow2, mul #16
>> +// CHECK-INST: uqdecw w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xfc,0xaf,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 fc af 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqincb w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqincb w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqincb wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqincb wsp
>> @@ -19,6 +14,25 @@ uqincb sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned inc only has one register operand)
>> +
>> +uqincb x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincb x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqincb w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincb w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqincb x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincb x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqincb.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqincb.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqincb.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqincb x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqincb w0
>> +// CHECK-INST: uqincb w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
>> +
>> +uqincb w0, all
>> +// CHECK-INST: uqincb w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
>> +
>> +uqincb w0, all, mul #1
>> +// CHECK-INST: uqincb w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
>> +
>> +uqincb w0, all, mul #16
>> +// CHECK-INST: uqincb w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 2f 04 <unknown>
>> +
>> +uqincb w0, pow2
>> +// CHECK-INST: uqincb w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf4,0x20,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f4 20 04 <unknown>
>> +
>> +uqincb w0, pow2, mul #16
>> +// CHECK-INST: uqincb w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf4,0x2f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f4 2f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqincd w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqincd w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqincd wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqincd wsp
>> @@ -19,6 +14,25 @@ uqincd sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned inc only has one register operand)
>> +
>> +uqincd x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincd x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqincd w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincd w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqincd x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincd x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqincd.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqincd.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqincd.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqincd x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqincd w0
>> +// CHECK-INST: uqincd w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
>> +
>> +uqincd w0, all
>> +// CHECK-INST: uqincd w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
>> +
>> +uqincd w0, all, mul #1
>> +// CHECK-INST: uqincd w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
>> +
>> +uqincd w0, all, mul #16
>> +// CHECK-INST: uqincd w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xf7,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 ef 04 <unknown>
>> +
>> +uqincd w0, pow2
>> +// CHECK-INST: uqincd w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf4,0xe0,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f4 e0 04 <unknown>
>> +
>> +uqincd w0, pow2, mul #16
>> +// CHECK-INST: uqincd w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf4,0xef,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f4 ef 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqinch w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqinch w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqinch wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqinch wsp
>> @@ -19,6 +14,25 @@ uqinch sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned inc only has one register operand)
>> +
>> +uqinch x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqinch x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqinch w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqinch w0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqinch x0, x0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqinch x0, x0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +
>> //
>> ------------------------------------------------------------------------- //
>> // Immediate not compatible with encode/decode function.
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqinch.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqinch.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqinch.s Mon Jun 18 13:50:33 2018
>> @@ -37,6 +37,47 @@ uqinch x0, all, mul #16
>>
>>
>> //
>> ---------------------------------------------------------------------------//
>> +// Test 32-bit form (w0) and its aliases
>> +//
>> ---------------------------------------------------------------------------//
>> +
>> +uqinch w0
>> +// CHECK-INST: uqinch w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
>> +
>> +uqinch w0, all
>> +// CHECK-INST: uqinch w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
>> +
>> +uqinch w0, all, mul #1
>> +// CHECK-INST: uqinch w0
>> +// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
>> +
>> +uqinch w0, all, mul #16
>> +// CHECK-INST: uqinch w0, all, mul #16
>> +// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: e0 f7 6f 04 <unknown>
>> +
>> +uqinch w0, pow2
>> +// CHECK-INST: uqinch w0, pow2
>> +// CHECK-ENCODING: [0x00,0xf4,0x60,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f4 60 04 <unknown>
>> +
>> +uqinch w0, pow2, mul #16
>> +// CHECK-INST: uqinch w0, pow2, mul #16
>> +// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]
>> +// CHECK-ERROR: instruction requires: sve
>> +// CHECK-UNKNOWN: 00 f4 6f 04 <unknown>
>> +
>> +
>> +//
>> ---------------------------------------------------------------------------//
>> // Test all patterns for 64-bit form
>> //
>> ---------------------------------------------------------------------------//
>>
>>
>> Modified: llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s?rev=334980&r1=334979&r2=334980&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s Mon Jun 18
>> 13:50:33 2018
>> @@ -3,11 +3,6 @@
>> //
>> ------------------------------------------------------------------------- //
>> // Invalid result register
>>
>> -uqincw w0
>> -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> -// CHECK-NEXT: uqincw w0
>> -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> -
>> uqincw wsp
>> // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
>> // CHECK-NEXT: uqincw wsp
>> @@ -19,6 +14,25 @@ uqincw sp
>> // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>>
>>
>> +//
>> ------------------------------------------------------------------------- //
>> +// Operands not matching up (unsigned inc only has one register operand)
>> +
>> +uqincw x0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
>> +// CHECK-NEXT: uqincw x0, w0
>> +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
>> +
>> +uqincw w0, w0
>> +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pa
>
>
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