[PATCH] D48485: [InstCombine] allow shl+mul combos with shuffle (select) fold (PR37806)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Transforms/InstCombine/InstCombineVectorOps.cpp:1177
+    // each vector element to determine if it is safe to keep that flag.
+    if (Opc0 == Instruction::Mul && Opc1 == Instruction::Shl) {
+      C1 = ConstantExpr::getShl(ConstantInt::get(C1->getType(), 1), C1);
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spatel wrote:
> RKSimon wrote:
> > Is this going to scale well? There's likely to be a lot of 'similar' cases (ADD x,x -> SHL x,1 etc.)
> That's what I wasn't sure about. I was guessing that add/sub was the common case, and we already canonicalize those. Can you list others? We can make some kind of map if there are a lot, but each case requires its own constant adjustment, so we'd end up with a switch I think.
ADD x,x -> SHL x,1 (or MUL x, 2)

AND x,0 -> MUL x,0 might happen (not sure - it probably disappears too early)

Also, merging OR x, c1 and ADD x, c2 if the carry bits don't clash (sorry, I've forgotten what this is called....) - similarly for OR x,c1 and XOR x,c2

UDIV and LSHR maybe (tricky.....)


https://reviews.llvm.org/D48485