[PATCH] D48439: [NEON] Support vldNq intrinsics in AArch32 (LLVM part)

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev created this revision.
kosarev added reviewers: SjoerdMeijer, jgreenhalgh, rengolin.
Herald added a reviewer: javed.absar.
Herald added a subscriber: kristof.beyls.

This patch adds support for the q versions of the dup (load-to-all-lanes) NEON intrinsics, such as vld2q_dup_f16() for example.

Currently, non-q versions of the dup intrinsics are implemented in clang by generating IR that first loads the elements of the structure into the first lane with the lane (to-single-lane) intrinsics, and then propagating it other lanes. There are at least two problems with this approach. First, there are no  double-spaced to-single-lane byte-element instructions. For example, there is no such instruction as 'vld2.8 { d0[0], d2[0] }, [r0]'. That means we cannot rely on the to-single-lane intrinsics and instructions to implement the q versions of the dup intrinsics. Note that to-all-lanes instructions do support all sizes of data items, including bytes.

The second problem with the current approach is that we need a separate vdup instruction to propagate the structure to each lane. So for vld4q_dup_f16() we would need four vdup instructions in addition to the initial vld instruction.

This patch introduces dup LLVM intrinsics and reworks handling of the currently supported (non-q) NEON dup intrinsics to expand them into those LLVM intrinsics, thus eliminating the need for using to-single-lane intrinsics and instructions.

Additionally, this patch adds support for u64 and s64 dup NEON intrinsics. These are marked as Arch64-only in the ARM NEON Reference, but it seems there are no reasons to not support them in AArch32 mode. Please correct, if that is wrong.

That's what we generate with this patch applied:

  vld2q_dup_f16:
    vld2.16 {d0[], d2[]}, [r0]
    vld2.16 {d1[], d3[]}, [r0]
  
  vld3q_dup_f16:
    vld3.16 {d0[], d2[], d4[]}, [r0]
    vld3.16 {d1[], d3[], d5[]}, [r0]
  
  vld4q_dup_f16:
    vld4.16 {d0[], d2[], d4[], d6[]}, [r0]
    vld4.16 {d1[], d3[], d5[], d7[]}, [r0]


https://reviews.llvm.org/D48439

Files:
  include/llvm/IR/IntrinsicsARM.td
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMExpandPseudoInsts.cpp
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMInstrNEON.td
  test/CodeGen/ARM/arm-vlddup.ll

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