[PATCH] D48128: [ARM] Parallel DSP IR Pass

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 152292.
SjoerdMeijer added a comment.

Yes, oops, fixed the alignment, and addressed the nits as well.

About:

> Could you please add an llc test to ensure that any unsafe ldrds don't get generated?

I was struggling creating a test case. The load/store optimiser runs after regalloc, and for it to trigger consecutive registers need to be loaded, which wasn't happening in my case. But I think this would be a fragile and indirect test. And perhaps more importantly, the alignment is now correctly set, to 2 in this case, and  I think we can rely on the load/store optimiser to respect this and do the right thing. That is, I see in the load/store optimiser pass that it is not capable operating on memory operations with getAlignment() < 4.


https://reviews.llvm.org/D48128

Files:
  lib/Target/ARM/ARM.h
  lib/Target/ARM/ARMParallelDSP.cpp
  lib/Target/ARM/ARMTargetMachine.cpp
  lib/Target/ARM/CMakeLists.txt
  lib/Target/ARM/LLVMBuild.txt
  test/CodeGen/ARM/smlad0.ll
  test/CodeGen/ARM/smlad1.ll
  test/CodeGen/ARM/smlad10.ll
  test/CodeGen/ARM/smlad2.ll
  test/CodeGen/ARM/smlad3.ll
  test/CodeGen/ARM/smlad4.ll
  test/CodeGen/ARM/smlad5.ll
  test/CodeGen/ARM/smlad6.ll
  test/CodeGen/ARM/smlad7.ll
  test/CodeGen/ARM/smlad8.ll
  test/CodeGen/ARM/smlad9.ll

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