[PATCH] D48086: [MIRParser] Update a diagnostic message to use the correct register sigil. NFC

[Matt Davis via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL335066: [MIRParser] Update a diagnostic message to use the correct register sigil. NFC (authored by mattd, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D48086?vs=150982&id=151960#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48086

Files:
  llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
  llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
  llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir


Index: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
@@ -23,7 +23,7 @@
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit %eflags'
+  ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit $eflags'
     JG_1 %bb.2.exit, implicit $eax
 
   bb.1.less:
Index: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
@@ -23,7 +23,7 @@
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit %eflags'
+  ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit $eflags'
     JG_1 %bb.2.exit, implicit-def $eflags
 
   bb.1.less:
Index: llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir
@@ -27,7 +27,7 @@
 
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags'
+  ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit $eflags'
     JG_1 %bb.2.exit
 
   bb.1.less:
Index: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
@@ -929,7 +929,7 @@
       continue;
     return error(Operands.empty() ? Token.location() : Operands.back().End,
                  Twine("missing implicit register operand '") +
-                     printImplicitRegisterFlag(I) + " %" +
+                     printImplicitRegisterFlag(I) + " $" +
                      getRegisterName(TRI, I.getReg()) + "'");
   }
   return false;


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