[PATCH] D45576: [RFC] Allow target to handle STRICT floating-point nodes

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand updated this revision to Diff 151936.
uweigand added a comment.
Herald added subscribers: qcolombet, MatzeB.

I've come up with a suggestion to avoid even the duplicated DAG patterns, by having them implicitly generated by TableGen.  This uses a new "alternative" mechanism described in a separate RFC:
https://reviews.llvm.org/D48326

Assuming this solution (or something along those lines) gets approved, this patch shows how we could use it to implement strict FP in back ends.  Note that the only back-end changes required for floating-point implicit are now:

- add an implicit Use of a register representing floating-point *control* state
- mark instructions as "mayAccessMemory" to indicate they may (or may not!) have a memory operand representing the floating-point *exception* state
- have the DAG pattern match e.g. "any_fadd", which is a new "alternative" of fadd and strict_fadd.

No duplication of any kind is expected.

Note that this patch is now *complete* (except for test cases).  As compared to the previous version, it additionally includes

- support for the FPC register
- support for all vector FP instructions
- the infrastructure to support optional memory operands (using the mayAccessMemory marker)


https://reviews.llvm.org/D45576

Files:
  include/llvm/CodeGen/MachineInstr.h
  include/llvm/CodeGen/MachineMemOperand.h
  include/llvm/CodeGen/PseudoSourceValue.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/MC/MCInstrDesc.h
  include/llvm/Target/Target.td
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/MIRParser/MILexer.cpp
  lib/CodeGen/MIRParser/MILexer.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MachineOperand.cpp
  lib/CodeGen/PseudoSourceValue.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Target/AMDGPU/R600InstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZInstrDFP.td
  lib/Target/SystemZ/SystemZInstrFP.td
  lib/Target/SystemZ/SystemZInstrVector.td
  lib/Target/SystemZ/SystemZOperators.td
  lib/Target/SystemZ/SystemZRegisterInfo.cpp
  lib/Target/SystemZ/SystemZRegisterInfo.td
  test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
  test/CodeGen/SystemZ/clear-liverange-spillreg.mir
  test/CodeGen/SystemZ/fp-cmp-07.mir
  test/CodeGen/SystemZ/fp-conv-17.mir
  test/CodeGen/SystemZ/fp-strict-add-01.ll
  utils/TableGen/CodeGenDAGPatterns.cpp
  utils/TableGen/CodeGenDAGPatterns.h
  utils/TableGen/CodeGenInstruction.cpp
  utils/TableGen/CodeGenInstruction.h
  utils/TableGen/DAGISelMatcherGen.cpp
  utils/TableGen/InstrInfoEmitter.cpp

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