[PATCH] D48321: [mips] Fix the predicates of some aliases

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
sdardis added reviewers: atanasyan, abeserminji, smaksimovic.
Herald added a subscriber: arichardson.

Previously, some aliases were marked as not being available for microMIPS32R6,
but this was overridden at the top level.


Repository:
  rL LLVM

https://reviews.llvm.org/D48321

Files:
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  lib/Target/Mips/MicroMipsInstrInfo.td
  test/MC/Mips/micromips32r6/valid.s


Index: test/MC/Mips/micromips32r6/valid.s
===================================================================
--- test/MC/Mips/micromips32r6/valid.s
+++ test/MC/Mips/micromips32r6/valid.s
@@ -401,7 +401,9 @@
   and $3, 5                # CHECK: andi $3, $3, 5         # encoding: [0xd0,0x63,0x00,0x05]
   and $3, $4, 5            # CHECK: andi $3, $4, 5         # encoding: [0xd0,0x64,0x00,0x05]
   not $3, $4               # CHECK: not $3, $4             # encoding: [0x00,0x04,0x1a,0xd0]
+                           # CHECK-NEXT:                   # <MCInst #{{.*}} NOR_MMR6
   not $3                   # CHECK: not $3, $3             # encoding: [0x00,0x03,0x1a,0xd0]
+                           # CHECK-NEXT:                   # <MCInst #{{.*}} NOR_MMR6
   or $3, 5                 # CHECK: ori $3, $3, 5          # encoding: [0x50,0x63,0x00,0x05]
   or $3, $4, 5             # CHECK: ori $3, $4, 5          # encoding: [0x50,0x64,0x00,0x05]
   xor $3, 5                # CHECK: xori $3, $3, 5         # encoding: [0x70,0x63,0x00,0x05]
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -1288,7 +1288,7 @@
 
 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
 
-let Predicates = [InMicroMips] in {
+let EncodingPredicates = [InMicroMips] in {
   def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
                                      II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
   def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
@@ -1375,10 +1375,10 @@
 
   def : MipsInstAlias<"not $rt, $rs",
                       (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
-        ISA_MICROMIPS;
+        ISA_MICROMIPS32_NOT_MIPS32R6;
   def : MipsInstAlias<"not $rt",
                       (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
-        ISA_MICROMIPS;
+        ISA_MICROMIPS32_NOT_MIPS32R6;
   def : MipsInstAlias<"bnez $rs,$offset",
                       (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
         ISA_MICROMIPS;
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -1677,6 +1677,9 @@
 def : MipsInstAlias<"not $rt, $rs",
                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
                     ISA_MICROMIPS32R6;
+def : MipsInstAlias<"not $rt",
+                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
+                    ISA_MICROMIPS32R6;
 def : MipsInstAlias<"lapc $rd, $imm",
                     (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
                     ISA_MICROMIPS32R6;


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