[llvm] r334922 - [X86] Add '.s' aliases to the assembler for the various redundant move encodings to match gas and our EVEX instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 17 22:00:50 PDT 2018
Author: ctopper
Date: Sun Jun 17 22:00:50 2018
New Revision: 334922
URL: http://llvm.org/viewvc/llvm-project?rev=334922&view=rev
Log:
[X86] Add '.s' aliases to the assembler for the various redundant move encodings to match gas and our EVEX instructions.
We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions.
Also remove the vpextrw.s EVEX alias. That's not something gas implements.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/MC/X86/x86-64-avx512bw.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=334922&r1=334921&r2=334922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Jun 17 22:00:50 2018
@@ -10601,9 +10601,6 @@ defm VPEXTRWZ : avx512_extract_elt_w<"vp
defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
-def : InstAlias<"vpextrw.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- (VPEXTRWZrr_REV GR32orGR64:$dst, VR128X:$src1, u8imm:$src2), 0>;
-
multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
X86VectorVTInfo _, PatFrag LdFrag> {
def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=334922&r1=334921&r2=334922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Jun 17 22:00:50 2018
@@ -1652,6 +1652,24 @@ def MOV64rr_REV : RI<0x8B, MRMSrcReg, (o
FoldGenData<"MOV64rr">;
}
+// Reversed version with ".s" suffix for GAS compatibility.
+def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}",
+ (MOV8rr_REV GR8:$dst, GR8:$src), 0>;
+def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}",
+ (MOV16rr_REV GR16:$dst, GR16:$src), 0>;
+def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}",
+ (MOV32rr_REV GR32:$dst, GR32:$src), 0>;
+def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}",
+ (MOV64rr_REV GR64:$dst, GR64:$src), 0>;
+def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
+ (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">;
+def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
+ (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">;
+def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
+ (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">;
+def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
+ (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">;
+
let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
"mov{b}\t{$src, $dst|$dst, $src}",
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=334922&r1=334921&r2=334922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Sun Jun 17 22:00:50 2018
@@ -206,9 +206,6 @@ def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSr
(ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
[]>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
-// These are 64 bit moves, but since the OS X assembler doesn't
-// recognize a register-register movq, we write them as
-// movd.
let isBitcast = 1 in {
def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
(outs GR64:$dst), (ins VR64:$src),
@@ -225,6 +222,9 @@ def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDes
} // SchedRW, hasSideEffects, isMoveReg
} // isBitcast
+def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
+ (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
(outs), (ins i64mem:$dst, VR64:$src),
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=334922&r1=334921&r2=334922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Jun 17 22:00:50 2018
@@ -212,6 +212,13 @@ multiclass sse12_move<RegisterClass RC,
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(store RC:$src, addr:$dst)], d>,
Sched<[WriteFStore]>;
+
+ def : InstAlias<"v"#OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ (!cast<Instruction>("V"#NAME#"rr_REV")
+ VR128:$dst, VR128:$src1, VR128:$src2), 0>;
+ def : InstAlias<OpcodeStr#".s\t{$src2, $dst|$dst, $src2}",
+ (!cast<Instruction>(NAME#"rr_REV")
+ VR128:$dst, VR128:$src2), 0>;
}
// Loading from memory automatically zeroing upper bits.
@@ -565,6 +572,24 @@ def : InstAlias<"vmovups\t{$src, $dst|$d
def : InstAlias<"vmovupd\t{$src, $dst|$dst, $src}",
(VMOVUPDYrr_REV VR256L:$dst, VR256H:$src), 0>;
+// Reversed version with ".s" suffix for GAS compatibility.
+def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}",
+ (VMOVAPSrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}",
+ (VMOVAPDrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}",
+ (VMOVUPSrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}",
+ (VMOVUPDrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}",
+ (VMOVAPSYrr_REV VR256:$dst, VR256:$src), 0>;
+def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}",
+ (VMOVAPDYrr_REV VR256:$dst, VR256:$src), 0>;
+def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}",
+ (VMOVUPSYrr_REV VR256:$dst, VR256:$src), 0>;
+def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}",
+ (VMOVUPDYrr_REV VR256:$dst, VR256:$src), 0>;
+
let SchedRW = [SchedWriteFMoveLS.XMM.MR] in {
def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
"movaps\t{$src, $dst|$dst, $src}",
@@ -597,6 +622,16 @@ let isCodeGenOnly = 1, ForceDisassemble
FoldGenData<"MOVUPDrr">;
}
+// Reversed version with ".s" suffix for GAS compatibility.
+def : InstAlias<"movaps.s\t{$src, $dst|$dst, $src}",
+ (MOVAPSrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"movapd.s\t{$src, $dst|$dst, $src}",
+ (MOVAPDrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"movups.s\t{$src, $dst|$dst, $src}",
+ (MOVUPSrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"movupd.s\t{$src, $dst|$dst, $src}",
+ (MOVUPDrr_REV VR128:$dst, VR128:$src), 0>;
+
let Predicates = [HasAVX, NoVLX] in {
// 256-bit load/store need to use floating point load/store in case we don't
// have AVX2. Execution domain fixing will convert to integer if AVX2 is
@@ -3350,6 +3385,22 @@ def : InstAlias<"vmovdqu\t{$src, $dst|$d
def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}",
(VMOVDQUYrr_REV VR256L:$dst, VR256H:$src), 0>;
+// Reversed version with ".s" suffix for GAS compatibility.
+def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}",
+ (VMOVDQArr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}",
+ (VMOVDQAYrr_REV VR256:$dst, VR256:$src), 0>;
+def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}",
+ (VMOVDQUrr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}",
+ (VMOVDQUYrr_REV VR256:$dst, VR256:$src), 0>;
+
+// Reversed version with ".s" suffix for GAS compatibility.
+def : InstAlias<"movdqa.s\t{$src, $dst|$dst, $src}",
+ (MOVDQArr_REV VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"movdqu.s\t{$src, $dst|$dst, $src}",
+ (MOVDQUrr_REV VR128:$dst, VR128:$src), 0>;
+
let Predicates = [HasAVX, NoVLX] in {
// Additional patterns for other integer sizes.
def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
@@ -4307,6 +4358,11 @@ def MOVPQI2QIrr : S2I<0xD6, MRMDestReg,
def : InstAlias<"vmovq\t{$src, $dst|$dst, $src}",
(VMOVPQI2QIrr VR128L:$dst, VR128H:$src), 0>;
+def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}",
+ (VMOVPQI2QIrr VR128:$dst, VR128:$src), 0>;
+def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
+ (MOVPQI2QIrr VR128:$dst, VR128:$src), 0>;
+
let Predicates = [UseAVX], AddedComplexity = 20 in {
def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
(VMOVQI2PQIrm addr:$src)>;
Modified: llvm/trunk/test/MC/X86/x86-64-avx512bw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64-avx512bw.s?rev=334922&r1=334921&r2=334922&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64-avx512bw.s (original)
+++ llvm/trunk/test/MC/X86/x86-64-avx512bw.s Sun Jun 17 22:00:50 2018
@@ -4691,54 +4691,6 @@
// CHECK: encoding: [0x62,0x62,0x7d,0xc9,0x7b,0xc0]
vpbroadcastw %eax, %zmm24 {%k1} {z}
-// CHECK: vpextrw $171, %xmm28, %eax
-// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0xab]
- vpextrw.s $0xab, %xmm28, %eax
-
-// CHECK: vpextrw $123, %xmm28, %eax
-// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0x7b]
- vpextrw.s $0x7b, %xmm28, %eax
-
-// CHECK: vpextrw $123, %xmm28, %r8d
-// CHECK: encoding: [0x62,0x43,0x7d,0x08,0x15,0xe0,0x7b]
- vpextrw.s $0x7b, %xmm28, %r8d
-
-// CHECK: vpextrw $171, %xmm28, %eax
-// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0xab]
- vpextrw.s $0xab, %xmm28, %eax
-
-// CHECK: vpextrw $123, %xmm28, %eax
-// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0x7b]
- vpextrw.s $0x7b, %xmm28, %eax
-
-// CHECK: vpextrw $123, %xmm28, %r8d
-// CHECK: encoding: [0x62,0x43,0x7d,0x08,0x15,0xe0,0x7b]
- vpextrw.s $0x7b, %xmm28, %r8d
-
-// CHECK: vpextrw $171, %xmm20, %eax
-// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xe0,0xab]
- vpextrw.s $0xab, %xmm20, %eax
-
-// CHECK: vpextrw $123, %xmm20, %eax
-// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xe0,0x7b]
- vpextrw.s $0x7b, %xmm20, %eax
-
-// CHECK: vpextrw $123, %xmm20, %r8d
-// CHECK: encoding: [0x62,0xc3,0x7d,0x08,0x15,0xe0,0x7b]
- vpextrw.s $0x7b, %xmm20, %r8d
-
-// CHECK: vpextrw $171, %xmm19, %eax
-// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xd8,0xab]
- vpextrw.s $0xab, %xmm19, %eax
-
-// CHECK: vpextrw $123, %xmm19, %eax
-// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xd8,0x7b]
- vpextrw.s $0x7b, %xmm19, %eax
-
-// CHECK: vpextrw $123, %xmm19, %r8d
-// CHECK: encoding: [0x62,0xc3,0x7d,0x08,0x15,0xd8,0x7b]
- vpextrw.s $0x7b, %xmm19, %r8d
-
// CHECK: vmovdqu16 %zmm19, %zmm22
// CHECK: encoding: [0x62,0xa1,0xff,0x48,0x7f,0xde]
vmovdqu16.s %zmm19, %zmm22
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=334922&r1=334921&r2=334922&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Sun Jun 17 22:00:50 2018
@@ -1635,6 +1635,126 @@ enclu
// CHECK: encoding: [0x0f,0x01,0xc0]
enclv
+// CHECK: movq %rax, %rbx
+// CHECK: encoding: [0x48,0x8b,0xd8]
+movq.s %rax, %rbx
+
+// CHECK: movq %rax, %rbx
+// CHECK: encoding: [0x48,0x8b,0xd8]
+mov.s %rax, %rbx
+
+// CHECK: movl %eax, %ebx
+// CHECK: encoding: [0x8b,0xd8]
+movl.s %eax, %ebx
+
+// CHECK: movl %eax, %ebx
+// CHECK: encoding: [0x8b,0xd8]
+mov.s %eax, %ebx
+
+// CHECK: movw %ax, %bx
+// CHECK: encoding: [0x66,0x8b,0xd8]
+movw.s %ax, %bx
+
+// CHECK: movw %ax, %bx
+// CHECK: encoding: [0x66,0x8b,0xd8]
+mov.s %ax, %bx
+
+// CHECK: movb %al, %bl
+// CHECK: encoding: [0x8a,0xd8]
+movb.s %al, %bl
+
+// CHECK: movb %al, %bl
+// CHECK: encoding: [0x8a,0xd8]
+mov.s %al, %bl
+
+// CHECK: movq %mm0, %mm1
+// CHECK: encoding: [0x0f,0x7f,0xc1]
+movq.s %mm0, %mm1
+
+// CHECK: movq %xmm0, %xmm1
+// CHECK: encoding: [0x66,0x0f,0xd6,0xc1]
+movq.s %xmm0, %xmm1
+
+// CHECK: movdqa %xmm0, %xmm1
+// CHECK: encoding: [0x66,0x0f,0x7f,0xc1]
+movdqa.s %xmm0, %xmm1
+
+// CHECK: movdqu %xmm0, %xmm1
+// CHECK: encoding: [0xf3,0x0f,0x7f,0xc1]
+movdqu.s %xmm0, %xmm1
+
+// CHECK: movaps %xmm0, %xmm1
+// CHECK: encoding: [0x0f,0x29,0xc1]
+movaps.s %xmm0, %xmm1
+
+// CHECK: movups %xmm0, %xmm1
+// CHECK: encoding: [0x0f,0x11,0xc1]
+movups.s %xmm0, %xmm1
+
+// CHECK: movapd %xmm0, %xmm1
+// CHECK: encoding: [0x66,0x0f,0x29,0xc1]
+movapd.s %xmm0, %xmm1
+
+// CHECK: movupd %xmm0, %xmm1
+// CHECK: encoding: [0x66,0x0f,0x11,0xc1]
+movupd.s %xmm0, %xmm1
+
+// CHECK: vmovq %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x79,0xd6,0xc0]
+vmovq.s %xmm0, %xmm8
+
+// CHECK: vmovq %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x79,0xd6,0xc0]
+vmovq.s %xmm8, %xmm0
+
+// CHECK: vmovdqa %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x79,0x7f,0xc0]
+vmovdqa.s %xmm0, %xmm8
+
+// CHECK: vmovdqa %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x79,0x7f,0xc0]
+vmovdqa.s %xmm8, %xmm0
+
+// CHECK: vmovdqu %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x7a,0x7f,0xc0]
+vmovdqu.s %xmm0, %xmm8
+
+// CHECK: vmovdqu %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x7a,0x7f,0xc0]
+vmovdqu.s %xmm8, %xmm0
+
+// CHECK: vmovaps %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x78,0x29,0xc0]
+vmovaps.s %xmm0, %xmm8
+
+// CHECK: vmovaps %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x78,0x29,0xc0]
+vmovaps.s %xmm8, %xmm0
+
+// CHECK: vmovups %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x78,0x11,0xc0]
+vmovups.s %xmm0, %xmm8
+
+// CHECK: vmovups %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x78,0x11,0xc0]
+vmovups.s %xmm8, %xmm0
+
+// CHECK: vmovapd %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x79,0x29,0xc0]
+vmovapd.s %xmm0, %xmm8
+
+// CHECK: vmovapd %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x79,0x29,0xc0]
+vmovapd.s %xmm8, %xmm0
+
+// CHECK: vmovupd %xmm0, %xmm8
+// CHECK: encoding: [0xc4,0xc1,0x79,0x11,0xc0]
+vmovupd.s %xmm0, %xmm8
+
+// CHECK: vmovupd %xmm8, %xmm0
+// CHECK: encoding: [0xc5,0x79,0x11,0xc0]
+vmovupd.s %xmm8, %xmm0
+
// __asm __volatile(
// "pushf \n\t"
// "popf \n\t"
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